White Electronic Designs
CFA45 Series CompactFlash
TM
CARDS
8MB to 512MB
PRODUCT DESCRIPTION
CFA45 series CompactFlash
TM
cards are built with NAND
flash memory components operating as solid-state disk.
They comply with the CompactFlash
TM
card standard
and are suitable for use as a data storage memory
medium for PCs or other electronic equipment. The
read/write unit is 1 sector (512 bytes) sequential access.
CompactFlash
TM
Cards
CFA45 Series
■
High performance:
Host data transfer rate
Flash data transfer rate
■
3 variations of mode access
Memory card mode
I/O card mode
True-IDE mode
■
Internal self-diagnostic program operates at V
CC
power on
■
High data reliability
Endurance: 100,000 Program / Erase cycles
High reliability based on internal ECC (Error
Correcting Code) function 2-bit ECC
Data reliability is 1 error in 10
14
bits read.
■
Power Consumption
Active mode
Idle mode
Stop mode
30 mA (typ.), 40 mA (max.)
10 mA
400 µA
20.0 MB/sec
10.0 MB/sec
■
Maximum card density is 512 MB
FEATURES
■
PC Card-ATA/True IDE/ I/O Card mode compatible
host interface
Automatic sensing of PC Card ATA and IDE mode
Included 256-byte CIS ROM
Support the five PC Card ATA addressing modes
Host Interface bus width: 8/16-bit Access
Flash Interface bus width: 8-bit Access
Support 3 power save mode: standby / idle / active
Auto power down function
2-bit ECC function
■
Operating Voltage: 3.3 V and 5.0 V
■
ISA standard and Read/Write unit is 512 bytes
(sector) sequential access
CARD BLOCK DIAGRAM
Vcc
GND
Internal Vcc
Data
In/Out
Host
Interface
Samsung
NAND
Flash
Samsung
Controller
Control
July 2003 Rev. 0
ECO #16318
1
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
I
NTERFACE
S
IGNALS
D
ESCRIPTION
Symbol
A
0
- A
10
Type
INPUT
Name and Function
CompactFlash
TM
Cards
CFA45 Series
ADDRESS BUS:
These address lines along with the REG signal are used to select the following: The I/O port
address registers within the PC Storage Card, the memory mapped port address registers within the PC
Storage Card, a byte in the Cards information structure and its configuration control and status registers. This
signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A [2:0]
are used to select the one of eight registers in the Task File, the remaining address lines should be grounded
by the host.
DATA BUS:
These signal lines carry the Data, Commands and Status information between the host and the
controller. D
0
is the LSB of the even byte of the word. D
8
is the LSB of the odd byte of the word.
This signal is the same as the PC Card memory mode signal in PC Card I/O mode. In True IDE mode, all Task
File operations occur in byte mode on the low order bus D
0
-D
7
while all data transfers are 16 bit using D
0
D
15
.
CARD ENABLE:
CE
1
and CE
2
are card select signals, active low. These input signals are used both to select
the card and to indicate to the card whether a byte or a word operation is being performed. CE
2
always
accesses the odd byte of the word. CE
1
accesses the even byte or the Odd byte of the word depending on
A
0
and CE
2
. A multiplexing scheme based on A
0
, CE
1
, CE
2
allows 8 bit hosts to access all data on
D
0
-D
7
. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE
mode, CE
1
is the chip select for the task file registers while CE
2
is used to select the Alternate Status
Register and the Device Control Register.
OUTPUT ENABLE, ATA SELECT:
OE is used for the control of data read in Attribute area or Common memory
area. To enable True IDE Mode this input should be grounded by the host (in power up).
WRITE ENABLE:
WE is used for the control of data write in Attribute memory area or Common memory area.
This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card
when the card is configured in the memory interface mode. It is also used for writing the configuration
registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode,
this input signal is not used and should be connected to VCC by the host.
I/O READ:
IORD is used for control of read data in the Task File area. This card does not respond to IORD
until I/O card interface setting up.
I/O WRITE:
IOWR is used for control of data write in the Task File area. This card does not respond to IOWR
until I/O card interface setting up. This signal is not used in memory mode. The I/O write strobe pulse is used
to clock I/O data on the card data bus into the CF Card controller registers when the CF Card is configured to
use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In
True IDE mode, this signal has the same function as in PC Card I/O Mode.
READY/BUSY, INTERRUPT REQUEST:
In memory mode, this signal is set high when the CF Card is
ready to accept a new data transfer operation and held low when the card is busy. The host memory card
socket must provide a pull-up resistor. At power up and at reset, the RDY/BSY signal is held low (busy) until
the CF Card has completed its power up or reset function. No access of any type should be made to the CF
Card during this time. The RDY/BSY signal is held high (disabled from being busy) whenever the following
condition is true: The CF Card has been powered up with RESET continuously disconnected or asserted. I/O
operation - After the CF Card has been configured for I/O operation, this signal is used as Interrupt request.
This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE
mode, this signal is the active high Interrupt request to the host.
CARD DETECTION:
CD
1
and CD
2
are the card detection signals. CD
1
and CD
2
are connected to ground in
this card, so the host can detect if the card is inserted or not.
WRITE PROTECT, 16 BIT I/O PORT:
In memory card mode, WP is held low because this card does not have a
write protect switch. In the I/O card mode, IOIS16 is asserted when Task File registers are accessed in 16-bit
mode. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer
cycle.
ATTRIBUTE MEMORY AREA SELECTION:
REG should be high level during common memory area accessing,
and low level during Attribute area accessing. The attribute memory area is located only in an even address, so
D
0
to D
7
are valid and D
8
to D
15
are invalid in the word access mode. Odd addresses are invalid in the byte
access mode. The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In
True IDE Mode this input signal is not used and should be connected to VCC.
BATTERY VOLTAGE DETECTION, DIGITAL AUDIO OUTPUT, DISK ACTIVE/SLAVE PRESENT:
In memory card
mode, BVD2 outputs the battery voltage status in the card. This card has no battery, so this output is high
level constantly. In the I/O card mode, SPKR is held High because this card does not have digital audio output.
In True IDE Mode DASP is the Disk Active/Slave Present signal in the Master/Slave handshake protocol.
RESET:
By assertion of the RESET signal, all registers of this card are cleared and the RDY/BSY signal turns
to high level. In True IDE Mode RESET is the active low hardware reset from the host.
4
D
0
- D
15
INPUT/
OUTPUT
CE
1
, CE
2
INPUT
OE, ASTEL
WE
INPUT
INPUT
IORD
IOWR
INPUT
INPUT
RDY/BSY,
IREQ, INTRQ
OUTPUT
CD
1
, CD
2
WP, IOIS16
OUTPUT
OUTPUT
REG
INPUT
BVD2, SPKR,
DASP
INPUT/
OUTPUT
RESET,
RESET
INPUT
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
White Electronic Designs
I
NTERFACE
S
IGNALS
D
ESCRIPTION CONT
.
Symbol
WAIT, IORDY
Type
OUTPUT
Name and Function
CompactFlash
TM
Cards
CFA45 Series
WAIT:
This signal outputs low level for the purpose of delaying memory access cycle or I/O access cycle. In
True IDE Mode this output signal may be used as IORDY. As for this controller, this output is high impedance
state constantly.
INPUT ACKNOWLEDGE:
This signal is not used in the memory card mode. The Input acknowledge signal is
asserted by the CF Card when the card is selected and responding to an I/O read cycle at the address that is
on the address bus. This signal is used by the host to control the enable of any input data buffers between the
CF Card and the CPU. In True IDE mode, this output signal is not used and should be connected to V
CC
at
the host.
BATTERY VOLTAGE DETECTION, STATUS CHANGE, PASS DIAGNOSTIC:
In the memory card mode, BVD1
outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly.
In the I/O card mode, STSCHG is used for changing the status of the Configuration status register in the
Attribute area, while the card is set I/O card interface. In True IDE Mode, PDIAG is the Pass Diagnostic signal
in the Master/Slave handshake protocol.
V
CC
VOLTAGE SENSE:
These signals are intended to notify the socket of the CF Cards CIS V
CC
requirement.
VS
1
is held low and VS
2
is not connected in this card.
CARD SELECT:
This signal is not used in the memory card mode and I/O card mode. This internally pulled up
signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When
this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as
a Slave.
INPACK
OUTPUT
BVD1,
STSCHG,
PDIAG
INPUT/
OUTPUT
VS
1
, VS
2
CSEL
OUTPUT
INPUT
COMPACTFLASH
TM
/PCMCIA-ATA REGISTER MAPPING ADDRESS.
C
OMPACT
F
LASH
TM
/PCMCIA-ATA I/O M
APPING
A
DDRESS
REG
L
L
L
L
L
L
L
L
L
L
L
L
L
Primary I/O
A[10:0]
1F0H
1F1H
1F2H
1F3H
1F4H
1F5H
1F6H
1F7H
-
-
-
3F6H
3F7H
Secondary I/O
A[10:0]
170H
171H
172H
173H
174H
175H
176H
177H
-
-
-
376H
377H
Independent I/O
A[3:0]
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
0DH
0EH
0FH
IORD = L
Read Even Data
Error Register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status Register
Duplicate Read Even Data
Duplicate Read Odd Data
Duplicate Error
Alternate Status
Drive Address
IOWR = L
Write Even Data
Feature Register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Command
Duplicate Write Even Data
Duplicate Write Odd Data
Duplicate Feature
Device Control
Reserved
5
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
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