74LVX161284MTDX_NL datasheet, PDF

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74LVX161284MTDX_NL: DescriptionLine Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size115KB，11 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74LVX161284MTDX_NL Overview

Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48

74LVX161284MTDX_NL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	CONTAINS EIGHT BIDIRECTIONAL DATA BUFFERS
Differential output	NO
Number of drives	14
Input properties	SCHMITT TRIGGER
Interface integrated circuit type	LINE TRANSCEIVER
Interface standards	IEEE 1284
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	12.5 mm
Humidity sensitivity level	2
Number of functions	13
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum receive delay	44 ns
Number of receiver bits	13
Maximum seat height	1.2 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
Supply voltage 1-max	5.5 V
Mains voltage 1-minute	3 V
Supply voltage1-Nom	3.15 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
maximum transmission delay	44 ns
width	6.1 mm
Base Number Matches	1

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74LVX161284 Low Voltage IEEE 161284 Translating Transceiver

January 1999

Revised June 2005

74LVX161284

Low Voltage IEEE 161284 Translating Transceiver

General Description

The LVX161284 contains eight bidirectional data buffers

and eleven control/status buffers to implement a full

IEEE 1284 compliant interface. The device supports the

IEEE 1284 standard and is intended to be used in an

Extended Capabilities Port mode (ECP). The pinout allows

for easy connection from the Peripheral (A-side) to the

Host (cable side).

Outputs on the cable side can be configured to be either

open drain or high drive (

14 mA) and are connected to a

separate power supply pin (V

-cable) to allow these out-

puts to be driven by a higher supply voltage than the A-

side. The pull-up and pull-down series termination resis-

tance of these outputs on the cable side is optimized to

drive an external cable. In addition, all inputs (except HLH)

and outputs on the cable side contain internal pull-up resis-

tors connected to the V

-cable supply to provide proper

termination and pull-ups for open drain mode.

Outputs on the Peripheral side are standard low-drive

CMOS outputs designed to interface with 3V logic. The DIR

input controls data flow on the A

–A

–B

transceiver

pins.

Features

Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

Translation capability allows outputs on the cable side to

interface with 5V signals

All inputs have hysteresis to provide noise margin

B and Y output resistance optimized to drive external

cable

B and Y outputs in high impedance mode during power

down

Inputs and outputs on cable side have internal pull-up

resistors

Flow-through pin configuration allows easy interface

between the “Peripheral and Host”

Replaces the function of two (2) 74ACT1284 devices

Ordering Code

Order Number

74LVX161284MEA

74LVX161284MTD

Package Number

MS48A

MTD48

Package Description

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

DIR

–A

–B

–A

–Y

–A

–C

PLH

HLH

Description

High Drive Enable Input (Active HIGH)

Direction Control Input

Inputs or Outputs

Inputs

Outputs

Inputs

Peripheral Logic HIGH Input

Peripheral Logic HIGH Output

Host Logic HIGH Input

Host Logic HIGH Output

DS500202

www.fairchildsemi.com

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