530AB1213M00BGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530AB1213M00BGR

530AB1213M00BGR: DescriptionLVPECL Output Clock Oscillator, 1213MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530AB1213M00BGR Overview

LVPECL Output Clock Oscillator, 1213MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AB1213M00BGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1213 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Circuit design of a common household appliance control module

Driver output control diagram

High-pass active filter circuit using LM110

73.333MHZ third harmonic circuit diagram

Dual dimming desk lamp circuit

The error I encountered when compiling wince6.0 system for the first time, about R3...: 错误如下： commctrl.lib(prsht.obj) : error LNK2019: unresolved external symbol CloseGestureInfoHandle referenced in function "int __cdecl PropSheetDlgProc(struct HWND__ *,unsigned int,unsigned int,long)" (...; jackysy99 Embedded System

Djyos shared the migration process from 2410 to 2440: I originally wanted to port DJYOS to LPC, but due to the requests of many netizens, I decided to port it to mini2440 first. For this purpose, I bought a mini2440 board. From 2410 to 2440, it should be...; flyshade Embedded System

BQ34Z100 operation process: [i=s]This post was last edited by qwqwqw2088 on 2020-2-15 16:38[/i]BQ34Z100 is a 1s to 16s Impedance Track power monitoring chip from TI First, let’s take a look at some key data in the BQ34Z100 data ...; qwqwqw2088 Analogue and Mixed Signal

[Uncle T's Library] "Computer Management and Maintenance Full Illustrated Guide": The book is divided into nine chapters, covering various problems that are likely to occur in computer software, hardware, network applications, etc., and provides detailed solutions. [color=rgb(51, 5...; tyw Download Centre

Constraints for asynchronous reset before synchronization?: An asynchronous reset signal is input from resetn_pad to a rstgen module for synchronization, and the output is rstout, which is the synchronization signal of sys_clk. However, the asynchronous reset ...; eeleader FPGA/CPLD

evc compilation error! ! Urgent! !: -------------------Configuration: SerialPort - Win32 (WCE ARMV4I) Debug-------------------- Compiling... PSerialPort.cpp c:\program files\windows ce tools\wce420\d200plus\mfc\include\afxdisp.h(72) : f...; sakura123 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components