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54LS161A DM54LS161A DM74LS161A 54LS163A DM54LS163A DM74LS163A Synchronous
4-Bit Binary Counters
May 1992
54LS161A DM54LS161A DM74LS161A
54LS163A DM54LS163A DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs The LS161A and LS163A are 4-bit binary counters
The carry output is decoded by means of a NOR gate thus
preventing spikes during the normal counting mode of oper-
ation Synchronous operation is provided by having all flip-
flops clocked simultaneously so that the outputs change co-
incident with each other when so instructed by the count-
enable inputs and internal gating This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform
These counters are fully programmable that is the outputs
may be preset to either level As presetting is synchronous
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input The clear function for the LS161A is asynchronous
and a low level at the clear input sets all four of the flip-flop
outputs low regardless of the levels of clock load or en-
able inputs The clear function for the LS163A is synchro-
nous and a low level at the clear inputs sets all four of the
flip-flop outputs low after the next clock pulse regardless of
the levels of the enable inputs This synchronous clear al-
lows the count length to be modified easily as decoding the
maximum count desired can be accomplished with one ex-
ternal NAND gate The gate output is connected to the clear
input to synchronously clear the counter to all low outputs
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output
Both count-enable inputs (P and T) must be high to count
and input T is fed forward to enable the ripple carry output
The ripple carry output thus enabled will produce a high-lev-
el output pulse with a duration approximately equal to the
high-level portion of the Q
A
output This high-level overflow
ripple carry pulse can be used to enable successive cascad-
ed stages High-to-low level transitions at the enable P or T
inputs may occur regardless of the logic level of the clock
These counters feature a fully independent clock circuit
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs The function of the counter (whether enabled dis-
abled loading or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Synchronously programmable
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Typical propagation time clock to Q output 14 ns
Typical clock frequency 32 MHz
Typical power dissipation 93 mW
Alternate
Military Aerospace
device
(54LS161
54LS163) is available Contact a National Semiconduc-
tor Sales Office Distributor for specificaitons
Connection Diagram
Dual-In-Line Package
Order Numbers 54LS161ADMQB 54LS161AFMQB
54LS161ALMQB 54LS163ADMQB 54LS163AFMQB
54LS163ALMQB DM54LS161AJ DM54LS161AW
DM54LS163AJ DM54LS163AW DM74LS161AM
DM74LS161AN DM74LS163AM or DM74LS163AN
See NS Package Number E20A J16A
M16A N16E or W16A
TL F 6397 – 1
C
1995 National Semiconductor Corporation
TL F 6397
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
Input Voltage
7V
7V
Note
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Operating Free Air Temperature Range
b
55 C to
a
125 C
DM54LS and 54LS
DM74LS
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
Parameter
Min
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
t
W
Pulse Width
(Note 1)
Pulse Width
(Note 2)
t
SU
Setup Time
(Note 1)
Clock
Clear
Clock
Clear
Data
Enable P
Load
Setup Time
(Note 2)
Data
Enable P
Load
t
H
Hold Time
(Note 1)
Hold Time
(Note 2)
t
REL
Data
Others
Data
Others
0
0
20
20
25
25
20
25
25
20
30
30
0
0
5
5
20
25
b
55
b
3
b
3
DM54LS161A
Nom
5
Max
55
Min
4 75
2
07
b
0 4
DM74LS161A
Nom
5
Max
5 25
Units
V
V
08
b
0 4
45
2
V
mA
mA
MHz
MHz
ns
4
25
20
6
9
0
0
20
20
25
25
8
17
15
20
25
25
20
30
30
0
0
5
5
20
25
125
0
b
3
b
3
8
25
20
6
9
ns
8
17
15
ns
ns
ns
ns
ns
ns
70
C
Clear Release Time (Note 1)
Clear Release Time (Note 2)
T
A
Free Air Operating Temperature
Note 1
C
L
e
15 pF R
L
e
2 kX T
A
e
25 C and V
CC
e
5 5V
Note 2
C
L
e
50 pF R
L
e
2 kX T
A
e
25 C and V
CC
e
5 5V
2
Talking
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