Freescale Semiconductor
Technical Data
Document Number: DSP56364
Rev. 4, 08/2006
DSP56364
24-Bit Audio Digital Signal Processor
1
Overview
Contents
1
2
3
4
5
6
A
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Signal/Connection Descriptions . . . . . . . . . 2-1
Specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Design Considerations . . . . . . . . . . . . . . . . 5-1
Ordering Information . . . . . . . . . . . . . . . . . . 6-1
IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
The DSP56364 supports digital audio applications
requiring sound field processing, acoustic equalization,
and other digital audio algorithms. The DSP56364 uses
the high performance, single-clock-per-cycle DSP56300
core family of programmable CMOS digital signal
processors (DSPs) combined with the audio signal
processing capability of the Freescale Symphony™ DSP
family, as shown in
Figure 1-1.
This design provides a
two-fold performance increase over Freescale’s popular
Symphony family of DSPs while retaining code
compatibility. Significant architectural enhancements
include a barrel shifter, 24-bit addressing, instruction
cache, and direct memory access (DMA). The
DSP56364 offers 100 million instructions per second
(MIPS) using an internal 100 MHz clock at 3.3 V.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Overview
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage*
V
IL
/ V
OL
V
IH
/ V
OH
V
IH
/ V
OH
V
IL
/ V
OL
Note:
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
4
12
5
GPIO
ESAI
SHI
PROGRAM RAM
0.5K x 24
PROGRAM ROM
8K x 24
X
MEMORY
RAM
1K X 24
Y
MEMORY
RAM
1.5K X 24
PIO_EB
PM_EB
XM_EB
YM_EB
PERIPHERAL
EXPANSION
AREA
ADDRESS
GENERATION UNIT
SIX CHANNELS
DMA UNIT
Bootstrap ROM
192 x 24
MEMORY
EXPANSION
AREA
ADDRESS
EXTERNAL
ADDRESS
BUS
SWITCH
18
YAB
XAB
PAB
DAB
24-BIT
DSP56300
CORE
DDB
INTERNAL
DATA BUS
SWITCH
YDB
XDB
PDB
GDB
DRAM & SRAM
BUS
INTERFACE
CONTROL
6
EXTERNAL
DATA BUS
SWITCH
DATA
8
POWER
MGMT
PLL
CLOCK
GEN
PROGRAM
INTERRUPT
CONT
PROGRAM
DECODE
CONT
PROGRAM
ADDRESS
GEN
DATA ALU
24 X 24+56
→
56-BIT MAC
TWO 56-BIT
ACCUMULATORS
BARREL SHIFTER
4
JTAG
OnCE™
EXTAL
MODA/IRQA
MODB/IRQB
MODD/IRQD
24 BITS BUS
RESET
PINIT/NMI
Figure 1-1 DSP56364 Block Diagram
DSP56364 Technical Data, Rev. 4
1-2
Freescale Semiconductor
Overview
1.1
1.1.1
•
•
•
•
•
•
•
•
•
•
Features
Digital Signal Processing Core
100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.
Object Code Compatible with the 56000 core.
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic
support.
Program Control with position independent code support and instruction cache support.
Six-channel DMA controller.
PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors
(1 to 16) and power saving clock divider (2
i
: i=0 to 7). Reduces clock noise.
Internal address tracing support and OnCE™ for Hardware/Software debugging.
JTAG port.
Very low-power CMOS design, fully static design with operating frequencies down to DC.
STOP and WAIT low-power standby modes.
1.1.2
•
•
•
•
•
On-chip Memory Configuration
1.5Kx24 Bit Y-Data RAM.
1Kx24 Bit X-Data RAM.
8Kx24 Bit Program ROM.
0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM.
0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25Kx24
Bit of Program RAM.
1.1.3
•
•
•
•
Off-chip memory expansion
External Memory Expansion Port with 8-bit data bus.
Off-chip expansion up to 2 x 16M x 8-bit word of Data/Program memory when using DRAM.
Off-chip expansion up to 2 x 256k x 8-bit word of Data/Program memory when using SRAM.
Simultaneous glueless interface to SRAM and DRAM.
1.1.4
•
Peripheral modules
Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmitt and 2
transmitt only, master or slave. I
2
S, Sony, AC97, network and other programmable protocols.
Unused pins of ESAI may be used as GPIO lines.
Serial Host Interface (SHI): SPI and I
2
C protocols, 10-word receive FIFO, support for 8, 16 and
24-bit words.
Four dedicated GPIO lines.
•
•
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
1-3
Overview
1.1.5
•
Packaging
100-pin plastic TQFP package.
1.2
Documentation
Table 1-1
lists the documents that provide a complete description of the DSP56364 and are required to
design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home
page on the Internet (the source for the latest information).
Table 1-1 DSP56364 Documentation
Document Name
DSP56300 Family Manual
Description
Detailed description of the 56000-family
architecture and the 24-bit core processor and
instruction set
Detailed description of memory, peripherals, and
interfaces
Brief description of the chip
Electrical and timing specifications; pin and
package descriptions
Order Number
DSP56300FM
DSP56364 User’s Manual
DSP56364 Product Brief
DSP56364 Technical Data Sheet
(this document)
DSP56364UM
DSP56364P
DSP56364
DSP56364 Technical Data, Rev. 4
1-4
Freescale Semiconductor
2
2.1
Signal/Connection Descriptions
Signal Groupings
The input and output signals of the DSP56364 are organized into functional groups, which are listed in
Table 2-1
and illustrated in
Figure 2-1.
The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.
Table 2-1 DSP56364 Functional Signal Groupings
Functional Group
Power (V
CC
)
Ground (GND)
Clock and PLL
Address bus
Data bus
Bus control
Interrupt and mode control
General Purpose I/O
SHI
ESAI
JTAG/OnCE Port
1
Number of
Signals
18
14
3
18
Port A
1
8
6
4
Port B
2
4
5
Port C
3
12
4
Detailed
Description
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-12
Table 2-9
Table 2-10
Table 2-11
Port A is the external memory interface port, including the external address bus, data bus, and control signals.
2
Port B signals are the GPIO signals.
3
Port C signals are the ESAI port signals multiplexed with the GPIO signals.
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
2-1
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