LTC6900
Low Power, 1kHz to 20MHz
Resistor Set SOT-23 Oscillator
FEATURES
s
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DESCRIPTIO
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One External Resistor Sets the Frequency
1kHz to 20MHz Frequency Range
500µA Typical Supply Current, V
S
= 3V, 3MHz
Frequency Error
≤1.5%
Max, 5kHz to 10MHz
(T
A
= 25°C)
Frequency Error
≤
2% Max, 5kHz to 10MHz
(T
A
= 0°C to 70°C)
±40ppm/°C
Temperature Stability
0.04%/V Supply Stability
50%
±1%
Duty Cycle 1kHz to 2MHz
50%
±5%
Duty Cycle 2MHz to 10MHz
Fast Start-Up Time: 50µs to 1.5ms
100Ω CMOS Output Driver
Operates from a Single 2.7V to 5.5V Supply
Low Profile (1mm) ThinSOT
TM
Package
The LTC
®
6900 is a precision, low power oscillator that is
easy to use and occupies very little PC board space. The
oscillator frequency is programmed by a single external
resistor (R
SET
). The LTC6900 has been designed for high
accuracy operation (≤1.5% frequency error) without the
need for external trim components.
The LTC6900 operates with a single 2.7V to 5.5V power
supply and provides a rail-to-rail, 50% duty cycle square
wave output. The CMOS output driver ensures fast rise/fall
times and rail-to-rail switching. The frequency-setting
resistor can vary from 10kΩ to 2MΩ to select a master
oscillator frequency between 100kHz and 20MHz (5V
supply). The three-state DIV input determines whether the
master clock is divided by 1, 10 or 100 before driving the
output, providing three frequency ranges spanning 1kHz
to 20MHz (5V supply). The LTC6900 features a proprietary
feedback loop that linearizes the relationship between
R
SET
and frequency, eliminating the need for tables to
calculate frequency. The oscillator can be easily pro-
grammed using the simple formula outlined below:
20k
f
OSC
=
10MHz
•
,
N
•
R
SET
100, DIV Pin
=
V
+
N
=
10, DIV Pin
=
Open
1 DIV Pin
=
GND
,
APPLICATIO S
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Portable and Battery-Powered Equipment
PDAs
Cell Phones
Low Cost Precision Oscillator
Charge Pump Driver
Switching Power Supply Clock Reference
Clocking Switched Capacitor Filters
Fixed Crystal Oscillator Replacement
Ceramic Oscillator Replacement
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
5V
0.1µF
10k
≤
R
SET
≤
2M
R
SET
vs Desired Output Frequency
10000
Clock Generator
1
2
3
V
+
1kHz
≤
f
OSC
≤
20MHz
5
5V, N = 100
4
N=1
1000
GND
SET
DIV
R
SET
(kΩ)
OUT
LTC6900
÷100
100
OPEN, N = 10
f
OSC
= 10MHz •
(
20k
N • R
SET
)
10
6900 TA01
1
1k
100k
1M
10M
10k
DESIRED OUTPUT FREQUENCY (Hz)
100M
U
÷10
÷1
6900 F02
U
U
6900f
1
LTC6900
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V
+
1
GND 2
SET 3
4 DIV
5 OUT
Supply Voltage (V
+
) to GND ........................– 0.3V to 6V
DIV to GND .................................... – 0.3V to (V
+
+ 0.3V)
SET to GND ................................... – 0.3V to (V
+
+ 0.3V)
Operating Temperature Range (Note 8)
LTC6900C .......................................... – 40°C to 85°C
LTC6900I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER
LTC6900CS5
LTC6900IS5
S5 PART MARKING
LTZM
S5 PACKAGE
5-LEAD PLASTIC SOT-23
T
JMAX
= 150°C,
θ
JA
= 256°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL
∆f
PARAMETER
Frequency Accuracy (Notes 2, 3)
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 2.7V to 5.5V, R
L
= 5k, C
L
= 5pF, Pin 4 = V
+
unless otherwise noted.
All voltages are with respect to GND.
CONDITIONS
V
+
= 5V
5kHz
≤
f
≤
10MHz
5kHz
≤
f
≤
10MHz, LTC6900C
5kHz
≤
f
≤
10MHz, LTC6900I
1kHz
≤
f < 5kHz
10MHz < f
≤
20MHz
5kHz
≤
f
≤
10MHz
5kHz
≤
f
≤
10MHz, LTC6900C
5kHz
≤
f
≤
10MHz, LTC6900I
1kHz
≤
f < 5kHz
V
+
= 5V
V
+
= 3V
q
q
q
q
MIN
TYP
±0.5
±2
±2
±0.5
MAX
±1.5
±2.0
±2.5
UNITS
%
%
%
%
%
%
%
%
%
kΩ
kΩ
%/°C
%/V
%
%
%
ppm/√kHr
V
+
= 3V
q
q
±2
20
20
±0.004
0.04
0.1
0.2
0.6
300
q
q
q
±1.5
±2.0
±2.5
400
400
0.1
R
SET
∆f/∆T
∆f/∆V
Frequency-Setting Resistor Range
Freq Drift Over Temp (Note 3)
Freq Drift Over Supply (Note 3)
Timing Jitter (Note 4)
∆f
< 1.5%
R
SET
= 63.2k
V
+
= 3V to 5V, R
SET
= 63.2k
Pin 4 = V
+
, 20k
≤
R
SET
≤
400k
Pin 4 = Open, 20k
≤
R
SET
≤
400k
Pin 4 = 0V, 20k
≤
R
SET
≤
400k
Pin 4 = V
+
or Open (DIV Either by 100 or 10)
Pin 4 = 0V (DIV by 1), R
SET
= 20k to 400k
R
SET
= 400k, Pin 4 = V
+
, R
L
=
∞
f
OSC
= 5kHz
R
SET
= 20k, Pin 4 = 0V, R
L
=
∞
f
OSC
= 10MHz
V
+
= 5V
V
+
= 3V
V
+
= 5V
V
+
= 3V
Long-Term Stability of Output Frequency
Duty Cycle (Note 7)
V
+
I
S
Operating Supply Range
Power Supply Current
49
45
2.7
50
50
0.32
0.29
0.92
0.68
51
55
5.5
0.42
0.38
1.20
0.86
0.5
q
q
q
q
q
V
+
– 0.4
q
V
IH
V
IL
I
DIV
High Level DIV Input Voltage
Low Level DIV Input Voltage
DIV Input Current (Note 5)
Pin 4 = V
+
Pin 4 = 0V
V
+
= 5V
V
+
= 5V
q
q
–4
2
–2
4
2
U
%
%
V
mA
mA
mA
mA
V
V
µA
µA
6900f
W
U
U
W W
W
LTC6900
ELECTRICAL CHARACTERISTICS
SYMBOL
V
OH
PARAMETER
High Level Output Voltage (Note 5)
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 2.7V to 5.5V, R
L
= 5k, C
L
= 5pF, Pin 4 = V
+
unless otherwise noted.
All voltages are with respect to GND.
CONDITIONS
V
+
= 5V
V
+
= 3V
V
OL
Low Level Output Voltage (Note 5)
V
+
= 5V
V
+
= 3V
t
r
OUT Rise Time
(Note 6)
V
+
= 5V
V
+
= 3V
t
f
OUT Fall Time
(Note 6)
V
+
= 5V
V
+
= 3V
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
Frequencies near 100kHz and 1MHz may be generated using two
different values of R
SET
(see the Selecting the Divider Setting Resistor
paragraph in the Applications Information section). For these frequencies,
the error is specified under the following assumption: 20k < R
SET
≤
200k.
Note 3:
Frequency accuracy is defined as the deviation from the
f
OSC
equation.
Note 4:
Jitter is the ratio of the peak-to-peak distribution of the period to
the mean of the period. This specification is based on characterization and
is not 100% tested. Also, see the Peak-to-Peak Jitter vs Output Frequency
curve in the Typical Performance Characteristics section.
Note 5:
To conform with the Logic IC Standard convention, current out of
a pin is arbitrarily given as a negative value.
I
OH
= – 1mA
I
OH
= – 4mA
I
OH
= – 1mA
I
OH
= – 4mA
I
OL
= 1mA
I
OL
= 4mA
I
OL
= 1mA
I
OL
= 4mA
Pin 4 = V
+
or Floating, R
L
=
∞
Pin 4 = 0V, R
L
=
∞
Pin 4 = V
+
or Floating, R
L
=
∞
Pin 4 = 0V, R
L
=
∞
Pin 4 = V
+
or Floating, R
L
=
∞
Pin 4 = 0V, R
L
=
∞
Pin 4 = V
+
or Floating, R
L
=
∞
Pin 4 = 0V, R
L
=
∞
q
q
q
q
q
q
q
q
MIN
4.8
4.5
2.7
2.2
TYP
4.95
4.8
2.9
2.6
0.05
0.2
0.1
0.4
14
7
19
11
13
6
19
10
MAX
UNITS
V
V
V
V
0.15
0.4
0.3
0.7
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
Note 6:
Output rise and fall times are measured between the 10% and
90% power supply levels. These specifications are based on
characterization.
Note 7:
Guaranteed by 5V test.
Note 8:
The LTC6900C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6900C is designed, characterized and expected to
meet specified performance from – 40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC6900I is guaranteed to meet
specified performance from – 40°C to 85°C.
6900f
3
LTC6900
TYPICAL PERFOR A CE CHARACTERISTICS
Frequency Variation vs R
SET
4
3
2
VARIATION (%)
T
A
= 25°C
GUARANTEED LIMITS APPLY OVER
20kΩ
≤
R
SET
≤
400kΩ
VARIATION (%)
1
0
–1
–2
–3
–4
1k
10k
0.25
0
–0.25
–0.50
–0.75
JITTER (%
P-P
)
TYPICAL HIGH
TYPICAL LOW
100k
R
SET
(Ω)
Supply Current vs Output
Frequency
2.0
T
A
= 25°C
C
L
= 5pF
SUPPLY CURRENT (mA)
1.5
÷10,
5V
÷100,
5V
1.0
OUTPUT RESISTANCE (Ω)
0.5
÷100,
3V
0
0
1k
÷10,
3V
÷1,
3V
10k
100k
1M
OUTPUT FREQUENCY (Hz)
4
U W
1M
6900 G01
Frequency Variation Over
Temperature
1.00
0.75
0.50
TYPICAL
HIGH
R
SET
= 63.4k
÷1
OR
÷10
OR
÷100
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–20
0
20
40
60
TEMPERATURE (°C)
80
6900 G02
Peak-to-Peak Jitter vs Output
Frequency
÷1,
V
A
= 5V
÷1,
V
A
= 3V
TYPICAL
LOW
÷10
÷100
1k
10k
100k
1M
OUTPUT FREQUENCY (Hz)
10M
6900 G03
–1.00
–40
0
Output Resistance
vs Supply Voltage
140
÷1,
5V
T
A
= 25°C
LTC6900 Output Operating at
20MHz, V
S
= 5V
V
+
= 5V, R
SET
= 10k, C
L
= 10pF
120
OUTPUT SOURCING CURRENT
100
1V/DIV
80
0V
60
OUTPUT SINKING CURRENT
40
12.5ns/DIV
6900 G06
10M
6900 G04
2.5
3.0
3.5 4.0 4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
6900 G05
LTC6900 Output Operating at
10MHz, V
S
= 3V
V
+
= 3V, R
SET
= 20k, C
L
= 10pF
1V/DIV
0V
25ns/DIV
6900 G07
6900f
LTC6900
PI FU CTIO S
V
+
(Pin 1):
Voltage Supply (2.7V
≤
V
+
≤
5.5V). This supply
must be kept free from noise and ripple. It should be
bypassed directly to a ground plane with a 0.1µF capacitor.
GND (Pin 2):
Ground. Should be tied to a ground plane for
best performance.
SET (Pin 3):
Frequency-Setting Resistor Input. The value
of the resistor connected between this pin and V
+
deter-
mines the oscillator frequency. The voltage on this pin is
held by the LTC6900 to approximately 1.1V below the V
+
voltage. For best performance, use a precision metal film
resistor with a value between 10kΩ and 2MΩ and limit the
capacitance on this pin to less than 10pF.
DIV (Pin 4):
Divider-Setting Input. This three-state input
selects among three divider settings, determining the
value of N in the frequency equation. Pin 4 should be tied
to GND for the
÷1
setting, the highest frequency range.
Floating Pin 4 divides the master oscillator by 10. Pin 4
should be tied to V
+
for the
÷100
setting, the lowest
frequency range. To detect a floating DIV pin, the LTC6900
attempts to pull the pin toward midsupply. Therefore,
driving the DIV pin high requires sourcing approximately
2µA. Likewise, driving DIV low requires sinking 2µA.
When Pin 4 is floated, it should preferably be bypassed by
a 1nF capacitor to ground or it should be surrounded by a
ground shield to prevent excessive coupling from other
PCB traces.
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ
and/or 10pF loads. Heavier loads may cause inaccuracies
due to supply bounce at high frequencies. Voltage tran-
sients, coupled into Pin 5, above or below the LTC6900
power supplies will not cause latchup if the current into/
out of the OUT pin is limited to 50mA.
BLOCK DIAGRA
1
R
SET
I
RES
3
V
+
SET
V
BIAS
2
GND
I
RES
THREE-STATE
INPUT DETECT
DIV
4
PATENT PENDING
W
U
U
U
V
RES
= (V
+
– V
SET
) = 1.1V TYPICALLY
+
GAIN = 1
MASTER OSCILLATOR
I
RES
ƒ
MO
= 10MHz • 20kΩ •
+
(V – V
SET
)
PROGRAMMABLE
DIVIDER (N)
(÷1, 10 OR 100)
OUT
V
+
5
–
DIVIDER
SELECT
+
–
2µA
+
–
GND
2µA
6900 BD
6900f
5
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