723614L20PQFI9 datasheet, PDF - EEWORLD Datasheet

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723614L20PQFI9: DescriptionPQFP-132, Tray; Categorystorage storage; File Size279KB，32 Pages; ManufacturerIDT (Integrated Device Technology)

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723614L20PQFI9 Overview

PQFP-132, Tray

723614L20PQFI9 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	PQFP
package instruction	QFP,
Contacts	132
Manufacturer packaging code	PQ132
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	12 ns
Other features	MAIL BOX; PARITY GENERATOR/CHECKER
period time	20 ns
JESD-30 code	S-PQFP-G132
JESD-609 code	e0
length	24.13 mm
memory density	2304 bit
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	132
word count	64 words
character code	64
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64X36
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	24.13 mm
Base Number Matches	1

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CMOS SyncBiFIFO

WITH

BUS-MATCHING AND BYTE SWAPPING

64 x 36 x 2

FEATURES:

•

IDT723614

•

Free-running CLKA and CLKB can be asynchronous or

coincident (simultaneous reading and writing of data on a

single clock edge is permitted)

Two independent clocked FIFOs (64 x 36 storage capacity each)

buffering data in opposite directions

Mailbox bypass Register for each FIFO

Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),

and 9 bits (byte)

Selection of Big- or Little-Endian format for word and byte bus

sizes

Three modes of byte-order swapping on port B

Programmable Almost-Full and Almost-Empty flags

Microprocessor interface control logic

EFA, FFA, AEA,

and

AFA

flags synchronized by CLKA

EFB, FFB, AEB,

and

AFB

flags synchronized by CLKB

Passive parity checking on each port

Parity generation can be selected for each port

Supports clock frequencies up to 67 MHz

Fast access times of 10 ns

Available in 132-pin plastic quad flat package (PQF) or space-

saving 120-pin thin quad flat package (TQFP)

Industrial temperature range (–40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

Mail 1

Parity

Gen/Check

MBF1

PEFB

PGB

Byte Matching &

Byte Swapping

Parity

Generation

Input

RAM

ARRAY

Output

RST

ODD/

EVEN

Device

Control

64 x 36

Write

Pointer

FFA

AFA

Read

Pointer

EFB

AEB

-B

Status Flag

Logic

FIFO1

Programmable Flag

Offset Register

FIFO2

Status Flag

Logic

Read

Pointer

Write

Pointer

FS0

FS1

- A

EFA

AEA

FFB

AFB

Bus Matching &

Byte Swapping

Parity

Generation

Output

RAM

ARRAY

64 x 36

PGA

Parity

Gen/Check

Mail 2

PEFA

MBF2

Input

Port-B

Control

Logic

CLKB

CSB

W/RB

ENB

SIZ0

SIZ1

SW0

SW1

3146 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

MARCH 2002

DSC-3146/1

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

™

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol

ODD/

EVEN

PEFA

Name

Odd/Even Parity

Select

Port A Parity Error

Flag

I/O

Description

Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when

ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity

generation is enabled for a read operation.

When any byte applied to terminals A0-A35 fails parity,

PEFA

is LOW. Bytes are organized as

A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the

parity bit. The type of parity checked is determined by the state of the ODD/EVEN input.

The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate

parity if parity generation is selected by PGA. Therefore, if a mail2 read parity generation is setup

by having W/RA LOW, MBA HIGH, and PGA HIGH, the

PEFA

flag is forced HIGH regardless of the

A0-A35 inputs.

When any valid byte applied to terminals B0-B35 fails parity,

PEFB

is LOW. Bytes are organized

as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity

bit. A byte is valid when it is used by the bus size selected for Port B. The type of parity checked is

determined by the state of the ODD/EVEN input.

The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if

parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by

having W/RB LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the

PEFB

flag is forced HIGH regardless

of the state of the B0-B35 inputs.

Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,

and A27-A35. The generated parity bits are output in the most significant bit of each byte.

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,

and B27-B35. The generated parity bits are output in the most significant bit of each byte.

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of

CLKB must occur while

RST

is LOW. This sets the

AFA, AFB, MBF1,

and

MBF2

flags HIGH and

the

EFA, EFB, AEA, AEB, FFA,

and

FFB

flags LOW. The LOW-to-HIGH transition of

RST

latches

the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offsets.

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and

BE,

and the following

LOW-to-HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes

can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for

a port B 36-bit write or read.

At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by

SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-

order swapping is possible with any bus-size selection.

A HIGH selects a write operation and a LOW selects a read operation on for a LOW-to-HIGH port A

transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.

A HIGH selects a write operation and a LOW selects a read operation on for a LOW-to-HIGH port B

B transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.

(Port A)

PEFB

Port B Parity Error

Flag

(Port B)

PGA

Port A Parity

Generation

Port B Parity

Generation

Reset

PGB

RST

SIZ0, SIZ1 Port B Bus Size

Selects

(Port B)

SW0, SW1

Port B byte Swap

Select

Port A Write/Read

Select

Port B Write/Read

Select

(Port B)

W/RA

W/RB

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