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5962-9458501HXX

Description
EEPROM Module, 128KX32, 300ns, Parallel, CMOS, HIP-66
Categorystorage    storage   
File Size380KB,43 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

5962-9458501HXX Overview

EEPROM Module, 128KX32, 300ns, Parallel, CMOS, HIP-66

5962-9458501HXX Parametric

Parameter NameAttribute value
MakerWhite Microelectronics
package instructionHIP-66
Reach Compliance Codeunknown
Maximum access time300 ns
Other featuresUSER CONFIGURABLE AS 512K X 8
Spare memory width16
JESD-30 codeS-XHIP-P66
JESD-609 codee0
length30.1 mm
memory density4194304 bit
Memory IC TypeEEPROM MODULE
memory width32
Number of functions1
Number of terminals66
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Package body materialUNSPECIFIED
encapsulated codeHIP
Package shapeSQUARE
Package formIN-LINE
Parallel/SerialPARALLEL
Programming voltage5 V
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height6.22 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationHEX
width30.1 mm
Maximum write cycle time (tWC)10 ms
Base Number Matches1
REVISIONS
LTR
E
DESCRIPTION
Added device type 06 for vendor cages 54230 and 88379. Added
vendor cage 0EU86 for device types 01 through 06. Figure 1,
changed case outline M to reflect package is available in either a
single or dual cavity. -sld
Added case outline 9.
Added device types 07, 08, and 09 for vendor cage 0EU86. Made
changes to table I to include the addition of device types 07, 08, and
09. Added a min limit to the table I for the I
LI
, and the I
LO
tests. Made
changes to Figures 2, 3, 4, 5, 6, and 8. -sld
Added case outline Z. Updated paragraph 1.2.4, 1.3, figures 1, 2,
and 8. -sld
Added case outline B. Added note to paragraph 1.2.4. -sld
DATE (YR-MO-DA)
99-05-14
APPROVED
K. A. Cottongim
F
G
00-04-06
02-01-31
Raymond Monnin
Raymond Monnin
H
J
02-06-04
03-10-06
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
J
35
J
15
J
36
J
16
J
17
J
18
REV
SHEET
PREPARED BY
Gary Zahn
CHECKED BY
Michael C. Jones
J
19
J
20
J
21
J
1
J
22
J
2
J
23
J
3
J
24
J
4
J
25
J
5
J
26
J
6
J
27
J
7
J
28
J
8
J
29
J
9
J
30
J
10
J
31
J
11
J
32
J
12
J
33
J
13
J
34
J
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
POST OFFICE BOX 3990
COLUMBUS, OHIO 43216-5000
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, 128K x 32-BIT, ELECTRICALLY
ERASABLE/PROGRAMMABLE READ ONLY
MEMORY
SIZE
A
SHEET
CAGE CODE
DRAWING APPROVAL DATE
94-08-02
REVISION LEVEL
J
67268
1 OF
36
5962-94585
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E009-04
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