IDT71V65903S80BG8 datasheet, PDF

Datasheet> All Categories > storage> storage> IDT71V65903S80BG8

IDT71V65903S80BG8: DescriptionZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119; Categorystorage storage; File Size491KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric Compare View All

IDT71V65903S80BG8 Overview

ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119

IDT71V65903S80BG8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	8 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	95 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

Preview

Download Datasheet

View All

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

Features

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

IDT71V65703

IDT71V65903

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

around between reads and writes, or writes and reads. Thus they have

been given the name ZBT

, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock

cycle, and on the next clock cycle the associated data cycle occurs, be it

read or write.

The IDT71V65703/5903 contain address, data-in and control signal

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CEN

is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write

is initiated.

The IDT71V65703/5903 have an on-chip burst counter. In the burst

mode, the IDT71V65703/5903 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO

input pin. The

LBO

pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Data Input/Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Asynchronous

Synchronous

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

DECEMBER 2002

DSC-5298/03

IDT71V65903S80BG8 Related Products

	IDT71V65903S80BG8	IDT71V65703S85BG8	IDT71V65903S75PFI8	IDT71V65703S80BG8	IDT71V65703S75BG8	IDT71V65903S75PF8	IDT71V65903S75BG8
Description	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 256KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	QFP	BGA	BGA	QFP	BGA
package instruction	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	14 X 22 MM, PLASTIC, MS-026AA, BGA-119
Contacts	119	119	100	119	119	100	119
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	8 ns	8.5 ns	7.5 ns	8 ns	7.5 ns	7.5 ns	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	95 MHz	90 MHz	100 MHz	95 MHz	100 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119
JESD-609 code	e0	e0	e0	e0	e0	e0	e0
length	22 mm	22 mm	20 mm	22 mm	22 mm	20 mm	22 mm
memory density	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	18	36	18	36	36	18	18
Humidity sensitivity level	3	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1	1
Number of terminals	119	119	100	119	119	100	119
word count	524288 words	262144 words	524288 words	262144 words	262144 words	524288 words	524288 words
character code	512000	256000	512000	256000	256000	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C	70 °C	70 °C	70 °C	70 °C
organize	512KX18	256KX36	512KX18	256KX36	256KX36	512KX18	512KX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	LQFP	BGA	BGA	LQFP	BGA
Encapsulate equivalent code	BGA119,7X17,50	BGA119,7X17,50	QFP100,.63X.87	BGA119,7X17,50	BGA119,7X17,50	QFP100,.63X.87	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	225	225	240	225	225	240	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.36 mm	2.36 mm	1.6 mm	2.36 mm	2.36 mm	1.6 mm	2.36 mm
Maximum standby current	0.04 A	0.04 A	0.06 A	0.04 A	0.04 A	0.04 A	0.04 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.25 mA	0.225 mA	0.295 mA	0.25 mA	0.275 mA	0.275 mA	0.275 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)
Terminal form	BALL	BALL	GULL WING	BALL	BALL	GULL WING	BALL
Terminal pitch	1.27 mm	1.27 mm	0.65 mm	1.27 mm	1.27 mm	0.65 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	QUAD	BOTTOM	BOTTOM	QUAD	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20	20	20	NOT SPECIFIED
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Is it lead-free?	Contains lead	Contains lead	-	Contains lead	Contains lead	-	-
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Base Number Matches	1	1	1	1	1	-	-

Recommended Resources

Fully automatic nickel-cadmium battery charging circuit composed of LM7806

Voltage controlled sawtooth oscillatora

Campus radio station automatic broadcast control circuit

Overview of three-terminal integrated voltage regulator

flash alarm circuit

Infrared receiving circuit

Debugging of full MOS operational amplifier circuit: For us novice analog IC designers, it is very helpful to learn how to debug the width-to-length ratio of existing MOS op amp circuits. However, it feels difficult to find a starting point at the begin...; linda_xia Power technology

Why does EVC programming fail to work when downloading via USB?: Why does the EVC programming fail to download via USB? How should I configure it?...; niuqing Embedded System

Award-winning live broadcast: ON Semiconductor's advanced packaging and drive technology helps silicon carbide energy applications. Registration is now open~: Award-winning live broadcast: ON Semiconductor's advanced packaging and drive technology helps silicon carbide energy applications. Registration is now open~Click here to register for the live broadca...; EEWORLD社区 Power technology

Later I found out that my prestige was negative even though I registered so early.: It seems that I will have to visit the forum more often and learn more in the future!...; cmj201003 Talking

Multisim simulation feels that the waveform is not right: Why isn’t the highest voltage of the waveform 27V? The lowest voltage should be 27-12V (regulated voltage) = 15V? [/font][/backcolor][/color] [color=#333333][backcolor=rgb(222, 240, 251)][font="] [/fo...; stm32f103vct6 Power technology

How can I define a variable in a C program whose address I know?: How can I define a variable in a C program whose address I know? What are the methods?...; ssky Analogue and Mixed Signal

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components