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841664AGILF

Description
TSSOP-28, Tube
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size630KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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841664AGILF Overview

TSSOP-28, Tube

841664AGILF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-28
Contacts28
Manufacturer packaging codeDQG28
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionClock Generators & Support Products 4 HCSL OUT SYNTHESIZER
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length9.7 mm
Humidity sensitivity level3
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency156.25 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP28,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency25 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate80 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width6.1 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
FemtoClock
®
Crystal-to-HCSL
Clock Generator
General Description
The ICS841664I is an optimized sRIO clock generator and a
member of the family of high-performance clock solutions from IDT.
The device uses a 25MHz parallel crystal to generate 125MHz and
156.25MHz clock signals, replacing solution requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (<1ps RMS) suitable to clock components requiring precise and
low-jitter sRIO clock signals. Designed for telecom, networking and
industrial application, the ICS841664I can also drive the high-speed
sRIO SerDes clock inputs of communication processors, DSPs,
switches and bridges.
ICS841664I
DATA SHEET
Features
Four differential HCSL clock outputs: configurable for sRIO
(125MHz or 156.25MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 125MHz or 156.25MHz
VCO: 625MHz
Supports PLL bypass and output enable functions
RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz):
0.45ps (typical) @ 125MHz
Full 3.3V power supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
Pin Assignment
V
DD
REF_OUT
GND
QA0
nQA0
V
DDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_ SEL
V
DDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IREF
FSEL0
FSEL1
QB0
nQB0
V
DDOB
GND
QB1
nQB1
MR/nOE
V
DD
XTAL _IN
XTAL_OUT
GND
XTAL_IN
25MHz
XTAL_OUT
REF_IN
REF_SEL
IREF
OSC
0
fref
1
QA0
nQA0
FemtoClock
PLL
VCO = 625MHz
0
÷ NA
Pulldown
1
QA1
nQA1
Pulldown
M = ÷25
QB0
nQB0
÷ NB
BYPASS
Pulldown
Pulldown
Pulldown
QB1
nQB1
FSEL[0:1]
MR/nOE
REF_OUT
nREF_OE
Pullup
ICS841664I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
ICS841664AGI REVISION A JULY 15, 2013
1
©2013 Integrated Device Technology, Inc.

841664AGILF Related Products

841664AGILF 841664AGILFT
Description TSSOP-28, Tube TSSOP-28, Reel
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction TSSOP-28 TSSOP-28
Contacts 28 28
Manufacturer packaging code DQG28 DQG28
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G28 R-PDSO-G28
JESD-609 code e3 e3
length 9.7 mm 9.7 mm
Humidity sensitivity level 3 3
Number of terminals 28 28
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Maximum output clock frequency 156.25 MHz 156.25 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP28,.3 TSSOP28,.3
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Master clock/crystal nominal frequency 25 MHz 25 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum slew rate 80 mA 80 mA
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 6.1 mm 6.1 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
Base Number Matches 1 1
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