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74F675ASCX_NL

Description
Serial In Parallel Out, F/FAST Series, 16-Bit, Right Direction, True Output, TTL, PDSO24, 0.300 INCH, LEAD FREE, PLASTIC, MS-013, SOIC-24
Categorylogic    logic   
File Size72KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

74F675ASCX_NL Overview

Serial In Parallel Out, F/FAST Series, 16-Bit, Right Direction, True Output, TTL, PDSO24, 0.300 INCH, LEAD FREE, PLASTIC, MS-013, SOIC-24

74F675ASCX_NL Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeSOIC
package instructionSOP,
Contacts24
Reach Compliance Codeunknown
Other featuresPARALLEL OUTPUT IS REGISTERED; READ/WRITE CONTROL; HOLD MODE
Counting directionRIGHT
seriesF/FAST
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length15.4 mm
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Number of digits16
Number of functions1
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
propagation delay (tpd)12 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width7.5 mm
minfmax85 MHz
Base Number Matches1
74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
April 1988
Revised October 2000
74F675A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F675A contains a 16-bit serial in/serial out shift reg-
ister and a 16-bit parallel out storage register. Separate
serial input and output pins are provided for expansion to
longer words. By means of a separate clock, the contents
of the shift register are transferred to the storage register.
The contents of the storage register can also be loaded
back into the shift register. A HIGH signal on the Chip
Select input prevents both shifting and parallel loading.
Features
s
Serial-to-parallel converter
s
16-Bit serial I/O shift register
s
16-Bit parallel out storage register
s
Recirculating parallel transfer
s
Expandable for longer words
s
Slim 24 lead package
s
74F675A version prevents false clocking through
CS or R/W inputs
Ordering Code:
Order Number
74F675ASC
74F675APC
74F675ASPC
Package Number
M24B
N24A
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS009587
www.fairchildsemi.com
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