The AD5383 is a complete, single-supply, 32-channel, 12-bit
DAC available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5383 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference, an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring, and an output amplifier boost mode
that allows optimization of the amplifier slew rate. The AD5383
contains a double-buffered parallel interface that features a
20 ns WR pulse width, an SPI/QSPI/MICROWIRE/DSP
compatible serial interface with interface speeds in excess of
30 MHz, and an I
2
C compatible interface that supports a
400 kHz data transfer rate.
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated indepen-
dently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC channel.
Power consumption is typically 0.25 mA/channel with boost
off.
Table 1. Other High Channel Count, Low Voltage, Single Supply DAC Products in Portfolio
Model
AD5380BST-5
AD5380BST-3
AD5384BBC-5
AD5384BBC-3
AD5381BST-5
AD5381BST-3
AD5382BST-5
AD5382BST-3
AD5390BST-5
AD5390BCP-5
AD5390BST-3
AD5390BCP-3
AD5391BST-5
AD5391BCP-5
AD5391BST-3
AD5391BCP-3
AD5392BST-5
AD5392BCP-5
AD5392BST-3
AD5392BCP-3
Resolution
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
AV
DD
Range
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
Output Channels
40
40
40
40
40
40
32
32
16
16
16
16
16
16
16
16
8
8
8
8
Linearity Error (LSB)
±4
±4
±4
±4
±1
±1
±4
±4
±3
±3
±3
±3
±1
±1
±1
±1
±3
±3
±3
±3
Package Description
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
Package Option
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
Table 2. 40-Channel, Bipolar Voltage Output DAC
Model
AD5379ABC
Resolution
14 Bits
Analog Supplies
±11.4 V to ±16.5 V
Output Channels
40
Linearity Error (LSB)
±3
Package
108-Lead CSPBGA
Package Option
BC-108
Rev. 0 | Page 3 of 40
AD5383
SPECIFICATIONS
AD5383-5 SPECIFICATIONS
Table 3. AV
DD
= 4.5 V to 5.5 V; DV
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V;
all specifications T
MIN
to T
MAX
, unless otherwise noted
Parameter
ACCURACY
Resolution
Relative Accuracy
2
(INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Offset Error
Offset Error TC
Gain Error
Gain Temperature Coefficient
3
DC Crosstalk
3
REFERENCE INPUT/OUTPUT
Reference Input
3
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output
4
Output Voltage
Reference TC
OUTPUT CHARACTERISTICS
3
Output Voltage Range
2
Short-Circuit Current
Load Current
Capacitive Load Stability
R
L
= ∞
R
L
= 5 kΩ
DC Output Impedance
MONITOR PIN
Output Impedance
Three-State Leakage Current
LOGIC INPUTS (EXCEPT SDA/SCL)
3
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
Input Current
Pin Capacitance
LOGIC INPUTS (SDA, SCL ONLY)
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
I
IN
, Input Leakage Current
V
HYST
, Input Hysteresis
C
IN
, Input Capacitance
Glitch Rejection
AD5383-5
1
12
±1
±1
±4
±4
±5
±0.024
±0.06
2
0.5
Unit
Bits
LSB max
LSB max
mV max
mV max
µV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
LSB max
Test Conditions/Comments
Guaranteed monotonic over temperature
Measured at Code 32 in the linear region
At 25°C
T
MIN
to T
MAX
2.5
1
±10
1 to V
DD
/2
V
MΩ min
µA max
V min/max
±1% for specified performance, AV
DD
= 2 × REFIN + 50 mV
Typically 100 MΩ
Typically ±30 nA
Enabled via CR8 in the AD5383 control register.
CR10 selects the reference voltage.
At ambient. Optimized for 2.5 V operation. CR10 = 1
1.25 V reference selected. CR10 = 0
2.495/2.505
1.22/1.28
±10
0/AV
DD
40
±1
200
1000
0.5
500
100
2
0.8
±10
10
0.7 DV
DD
0.3 DV
DD
±1
0.05 DV
DD
8
50
V min/max
V min/max
ppm/°C typ
V min/max
mA max
mA max
pF max
pF max
Ω max
Ω typ
nA typ
DV
DD
= 2.7 V to 5.5 V
V min
V max
µA max
pF max
V min
V max
µA max
V min
pF typ
ns max
Total for all pins. T
A
= T
MIN
to T
MAX
SMBus compatible at DV
DD
< 3.6 V
SMBus compatible at DV
DD
< 3.6 V
Input filtering suppresses noise spikes of less than 50 ns
Rev. 0 | Page 4 of 40
AD5383
Parameter
LOGIC OUTPUTS (BUSY, SDO)
3
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)
3
V
OL
, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AV
DD
DV
DD
Power Supply Sensitivity
3
∆Midscale/∆ΑV
DD
AI
DD
DI
DD
AI
DD
(Power-Down)
DI
DD
(Power-Down)
Power Dissipation
AD5383-5
1
0.4
DV
DD
– 1
0.4
DV
DD
– 0.5
±1
5
0.4
0.6
±1
8
4.5/5.5
2.7/5.5
–85
0.375
0.475
1
2
20
65
Unit
V max
V min
V max
V min
µA max
pF typ
V max
V max
µA max
pF typ
V min/max
V min/max
dB typ
mA/channel max
mA/channel max
mA max
µA max
µA max
mW max
Test Conditions/Comments
DV
DD
= 5 V ± 10%, sinking 200 µA
DV
DD
= 5 V ± 10%, sourcing 200 µA
DV
DD
= 2.7 V to 3.6 V, sinking 200 µA
DV
DD
= 2.7 V to 3.6 V, sourcing 200 µA
SDO only
SDO only
I
SINK
= 3 mA
I
SINK
= 6 mA
Outputs unloaded, Boost off. 0.25 mA/channel typ
Outputs unloaded, Boost on. 0.325 mA/channel typ
V
IH
= DV
DD
, V
IL
= DGND.
Typically 200 nA
Typically 3 µA
Outputs unloaded, Boost off, AV
DD
= DV
DD
= 5 V
1
2
AD5383-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.
Accuracy guaranteed from V
OUT
= 10 mV to AV
DD
– 50 mV.
3
Guaranteed by characterization, not production tested.
4
Default on the AD5383-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5383 control register; operating the AD5383-5 with a 1.25 V reference will lead to
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Embedded System
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