74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
Rev. 8 — 5 February 2016
Product data sheet
1. General description
The 74HC4051; 74HCT4051 is a single-pole octal-throw analog switch (SP8T) suitable for
use in analog or digital 8:1 multiplexer/demultiplexer applications. The switch features
three digital select inputs (S0, S1 and S2), eight independent inputs/outputs (Yn), a
common input/output (Z) and a digital enable input (E). When E is HIGH, the switches are
turned off. Inputs include clamp diodes. This enables the use of current limiting resistors
to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Wide analog input voltage range from
5
V to +5 V
Complies with JEDEC standard no. 7A
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4051D
74HCT4051D
74HC4051DB
74HCT4051DB
74HC4051PW
74HCT4051PW
74HC4051BQ
74HCT4051BQ
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
Fig 1.
Functional diagram
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 5 February 2016
2 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Fig 4.
Schematic diagram (one switch)
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 5 February 2016
3 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5.
Pin configuration SO16, and (T)SSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
E
V
EE
GND
S0, S1, S2
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
Z
V
CC
Pin description
Pin
6
7
8
11, 10, 9
13, 14, 15, 12, 1, 5, 2, 4
3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 5 February 2016
4 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3.
Input
E
L
L
L
L
L
L
L
L
H
[1]
Function table
[1]
Channel ON
S2
L
L
L
L
H
H
H
H
X
S1
L
L
H
H
L
L
H
H
X
S0
L
H
L
H
L
H
L
H
X
Y0 to Z
Y1 to Z
Y2 to Z
Y3 to Z
Y4 to Z
Y5 to Z
Y6 to Z
Y7 to Z
switches off
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
P
[1]
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
power dissipation
Conditions
[1]
Min
0.5
-
-
-
-
-
-
65
Max
+11.0
20
20
25
20
50
50
+150
500
100
Unit
V
mA
mA
mA
mA
mA
mA
C
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
0.5
V < V
SW
< V
CC
+ 0.5 V
SO16, (T)SSOP16, and
DHVQFN16 package
per switch
[2]
-
-
To avoid drawing V
CC
current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no V
CC
current will flow out of terminals Yn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed V
CC
or V
EE
.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 8 — 5 February 2016
5 of 31
京公网安备 11010802033920号
EEWORLD
