74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 9 — 10 February 2016
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a triple single-pole double-throw analog switch (3x SPDT)
suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch
features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a
common input/output (nZ). A digital enable input (E) is common to all switches. When E is
HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Wide analog input voltage range from
5
V to +5 V
Complies with JEDEC standard no. 7A
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4053D
74HCT4053D
74HC4053DB
74HCT4053DB
74HC4053PW
74HCT4053PW
74HC4053BQ
74HCT4053BQ
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
Fig 1.
Functional diagram
74HC_HCT4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 9 — 10 February 2016
2 of 31
NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Fig 4.
Schematic diagram (one switch)
74HC_HCT4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 9 — 10 February 2016
3 of 31
NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5.
Pin configuration SO16, and (T)SSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
E
V
EE
GND
S1, S2, S3
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z, 2Z, 3Z
V
CC
Pin description
Pin
6
7
8
11, 10, 9
12, 2, 5
13, 1, 3
14, 15, 4
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
independent input or output
common output or input
supply voltage
74HC_HCT4053
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 9 — 10 February 2016
4 of 31
NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
7. Functional description
Table 3.
Inputs
E
L
L
H
[1]
Function table
[1]
Channel on
Sn
L
H
X
nY0 to nZ
nY1 to nZ
switches off
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
P
[1]
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
power dissipation
Conditions
[1]
Min
0.5
-
-
-
-
-
-
65
Max
+11.0
20
20
25
20
50
50
+150
500
100
Unit
V
mA
mA
mA
mA
mA
mA
C
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
0.5
V < V
SW
< V
CC
+ 0.5 V
SO16, (T)SSOP16, and
DHVQFN16 package
per switch
[2]
-
-
To avoid drawing V
CC
current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no V
CC
current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed V
CC
or V
EE
.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
9. Recommended operating conditions
Table 5.
Symbol
V
CC
Recommended operating conditions
Parameter
supply voltage
Conditions
Min
see
Figure 7
and
Figure 8
V
CC
GND
V
CC
V
EE
V
I
V
SW
74HC_HCT4053
74HC4053
Typ
Max
Min
74HCT4053
Typ
Max
Unit
2.0
2.0
GND
V
EE
5.0
5.0
-
-
10.0
10.0
V
CC
V
CC
4.5
2.0
GND
V
EE
5.0
5.0
-
-
5.5
10.0
V
CC
V
CC
V
V
V
V
input voltage
switch voltage
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 9 — 10 February 2016
5 of 31
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