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74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
Rev. 8 — 3 December 2015
Product data sheet
1. General description
The 74HC4066; 74HCT4066 is a quad single pole, single throw analog switch. Each
switch features two input/output terminals (nY and nZ) and an active HIGH enable input
(nE). When nE is LOW, the analog switch is turned off. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2. Features and benefits
Input levels nE inputs:
For 74HC4066: CMOS level
For 74HCT4066: TTL level
Low ON resistance:
50
(typical) at V
CC
= 4.5 V
45
(typical) at V
CC
= 6.0 V
35
(typical) at V
CC
= 9.0 V
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4066D
74HCT4066D
74HC4066DB
74HCT4066DB
74HC4066PW
74HCT4066PW
74HC4066BQ
74HCT4066BQ
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
SSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
Version
SOT108-1
SOT337-1
Type number
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Schematic diagram (one switch)
74HC_HCT4066
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 8 — 3 December 2015
2 of 24
NXP Semiconductors
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 4.
Pin configuration for SO14 and (T)SSOP14
Fig 5.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Z, 2Z, 3Z, 4Z
1Y, 2Y, 3Y, 4Y
GND
1E, 2E, 3E, 4E
V
CC
Pin description
Pin
2, 3, 9, 10
1, 4, 8, 11
7
13, 5, 6, 12
14
Description
independent input or output
independent input or output
ground (0 V)
enable input (active HIGH)
supply voltage
6. Functional description
Table 3.
Input nE
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Switch
OFF
ON
74HC_HCT4066
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 8 — 3 December 2015
3 of 24
NXP Semiconductors
74HC4066; 74HCT4066
Quad single-pole single-throw analog switch
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO14, (T)SSOP14 and DHVQFN14
packages
P
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
V
SW
=
0.5
V to V
CC
+ 0.5 V
[1]
Min
0.5
-
-
-
-
-
65
-
-
Max
+11.0
20
20
25
50
50
+150
500
100
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
power dissipation
per switch
To avoid drawing V
CC
current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no V
CC
current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed V
CC
or GND.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
[2]
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Conditions
Min
V
CC
V
I
V
SW
T
amb
t/V
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
CC
= 10.0 V
2.0
GND
GND
40
-
-
-
-
74HC4066
Typ
5.0
-
-
+25
-
1.67
-
-
Max
10.0
V
CC
V
CC
+125
625
139
83
35
Min
4.5
GND
GND
40
-
-
-
-
74HCT4066
Typ
5.0
-
-
+25
-
1.67
-
-
Max
5.5
V
CC
V
CC
+125
-
139
-
-
V
V
V
C
ns/V
ns/V
ns/V
ns/V
Unit
Symbol Parameter
74HC_HCT4066
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 8 — 3 December 2015
4 of 24
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