530EA99M0000BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530EA99M0000BG

530EA99M0000BG: DescriptionLVPECL Output Clock Oscillator, 99MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530EA99M0000BG Overview

LVPECL Output Clock Oscillator, 99MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530EA99M0000BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	99 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

Six output circuit diagrams of integrated speed/voltage converter LM2907/2917

Acousto-optic digital level detector circuit diagram

Large signal diode detection circuit

Motor automatic adjustment power circuit

Crystal oscillator using op amp 2

Automatic zero calibration amplifier circuit

EEWORLD University - What is Dynamic Multi-Protocol Manager (DMM)?: What is Dynamic Multiprotocol Manager (DMM) : https://training.eeworld.com.cn/course/5257This training will cover the fundamentals of using DMM (Dynamic Multi-protocol Manager), a software module that...; hi5 Talking

Does the ZIGBEE antenna made by CC2530+CC2591 need to add an electrostatic protection device?: Now the antenna of ZIGBEE is external, and an electrostatic protection device is added to the antenna end. For example, a TVS tube. Can you recommend a TVS tube model? 0402 package....; wanggang1006 RF/Wirelessly

How to chat with Indians in English: Today, an Indian uncle consulted me about BBB LCD cape through QQ. The whole communication was in English, no pressure at all! [size=14px]Youdao is a magical tool, haha. [/size] [size=14px] [/size] Wh...; chenzhufly Talking

Code Help: architecture beeper of div issignal count : std_logic_vector(0 to 25);signal true : std_logic:='0';beginprocess(clk)beginif (rising_edge(clk)) thenif true='0' thenif (rst='0')thencount'0');true<='1';e...; 4027379 FPGA/CPLD

Single document window cannot be restored from the tray area: It should be that after receiving the tray area message, AfxGetMainWnd()->ShowWindow(SW_SHOW); can be used in the dialog application. It can now be a single document, but it is not reflected in the se...; lizengmao Embedded System

git-flow cheat sheet: ...; qinkaiabc Programming Basics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components