Document Revision History
Version History
Rev 0.0
Rev 1.0
Initial release
Fixed typos in Section 1.1.3; Replace any reference to Flash Interface Unit with Flash
Memory Module; added note to Vcap pin in
Table 2-2;
corrected
Table 4-4,
removed
unneccessary notes in
Table 10-12;
corrected temperature range in
Table 10-14;
added
ADC calibration information to
Table 10-23
and new graphs in
Figure 10-21
Corrected 2.2μF to 0.1
μF
low ESR capacitor in
Table 2-2.
Replaced
Table 10-16
with
correct parameters for the 128 package pinout. Corrected (fout/2) with (fout) in
Table 10-14.
Corrected pinout labels in
Figure 11-1.
Adding/clarifing notes to
Table 4-4
to help clarify independent program flash blocks and
other Program Flash modes, clarification to
Table 10-22,
corrected Digital Input Current Low
(pull-up enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note
to
Table 10-1.
Correcting
Table 4-6
Address locations.
Added 56F8155 information; edited to indicate differences in 56F8355 and 56F8155. Refor-
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout the family. Clarified I/O power
description in
Table 2-2,
added note to
Table 10-7
and clarified
Section 12.3.
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Updated
Table 10-23
to reflect new value for maximum Uncalibrated Gain Error
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial)
in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference
crystal frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
Corrected bootflash memory map layout in
Table 4-4
to 16KB.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a
debugging environment, TRST may be tied to V
SS
through a 1K resistor.
Description of Change
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev 11.0
Rev. 12
Please see http://www.freescale.com for the most current data sheet revision.
56F8355 Technical Data, Rev. 12
2
Freescale Semiconductor
Preliminary
56F8355/56F8155 General Description
Note:
Features in italics are NOT available in the 56F8155 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 256KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 16KB Data RAM
• 16KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
• Up to two Quadrature Decoders
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
RSTO
RESET
6
3
4
6
3
4
4
4
5
4
4
PWM Outputs
Current Sense Inputs
or
GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
Program Controller
and Hardware
Looping Unit
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP
4
V
DDA
2
V
SSA
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
AD1
VREF
PAB
PDB
CDBR
CDBW
ADCA
Memory
Program Memory
128K x 16 Flash
2K x 16 RAM
Boot ROM
8K x 16 Flash
Data Memory
4K x 16 Flash
8K x 16 RAM
R/W Control
AD0
AD1
ADCB
XDB2
XAB1
XAB2
PDB
CDBR
CDBW
Temp_Sense
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad Timer C
or GPIOE
Quad Timer D
or
GPIOE
FlexCAN
System Bus
Control
External Bus
Interface Unit
PAB
*
External
Address Bus
Switch
*
External
Data
Bus Switch
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
4
D7-10 or GPIOF0-3
IPBus Bridge (IPBB)
Decoding
Peripherals
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
*
Bus
Control
6
GPIOD0-5 or CS2-7
4
2
4
2
Clock
resets
P
System
O
Integration
R
Module
PLL
*
EMI not functional in
this package; use as
GPIO pins
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA
IRQB
CLKO
CLKMODE
56F8355/56F8155 Block Diagram
56F8355 Technical Data, Rev. 12
Freescale Semiconductor
Preliminary
3
Table of Contents
Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8355/56F8155 Features . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment9
1.4. Architecture Block Diagram . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions. . . . . . . . . . . . . 14
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 124
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 124
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . 124
8.3. Configuration . . . . . . . . . . . . . . . . . . . . 124
Part 9: Joint Test Action Group (JTAG) . . 129
9.1. 56F8355 Information . . . . . . . . . . . . . . 129
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . 18
Part 10: Specifications. . . . . . . . . . . . . . . . 129
10.1. General Characteristics . . . . . . . . . . . 129
10.2. DC Electrical Characteristics . . . . . . . 134
10.3. AC Electrical Characteristics . . . . . . . 138
10.4. Flash Memory Characteristics . . . . . . 138
10.5. External Clock Operation Timing . . . . 139
10.6. Phase Locked Loop Timing . . . . . . . . 139
10.7. Crystal Oscillator Timing . . . . . . . . . . 140
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . 140
10.9. Serial Peripheral Interface
(SPI) Timing . . . . . . . . . . . . . . 142
10.10. Quad Timer Timing . . . . . . . . . . . . . . 145
10.11. Quadrature Decoder Timing . . . . . . 146
10.12. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . 147
10.13. Controller Area Network (CAN) Timing 147
10.14. JTAG Timing. . . . . . . . . . . . . . . . . . . 148
10.15. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . 149
10.16. Equivalent Circuit for ADC Inputs . . 152
10.17. Power Consumption . . . . . . . . . . . . . 152
Part 3: On-Chip Clock Synthesis (OCCS) . . 34
3.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . 34
3.2. External Clock Operation . . . . . . . . . . . . 34
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 36
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 36
4.1. Introduction. . . . . . . . . . . . . . . . . . . . . . .
4.2. Program Map . . . . . . . . . . . . . . . . . . . . .
4.3. Interrupt Vector Table . . . . . . . . . . . . . .
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . .
4.5. Flash Memory Map. . . . . . . . . . . . . . . . .
4.6. EOnCE Memory Map . . . . . . . . . . . . . . .
4.7. Peripheral Memory Mapped Registers . .
4.8. Factory Programmed Memory . . . . . . . .
36
37
39
42
43
44
45
72
Part 5: Interrupt Controller (ITCN) . . . . . . . . 72
5.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . 72
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3. Functional Description . . . . . . . . . . . . . . 73
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . 75
5.5. Operating Modes . . . . . . . . . . . . . . . . . . 75
5.6. Register Descriptions . . . . . . . . . . . . . . . 76
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . 102
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 154
11.1. 56F8355 Package and Pin-Out
Information . . . . . . . . . . . . . . . . 154
11.2. 56F8155 Package and Pin-Out
Information . . . . . . . . . . . . . . . 157
Part 6: System Integration Module (SIM) . 103
6.1. Overview. . . . . . . . . . . . . . . . . . . . . . . . 103
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3. Operating Modes . . . . . . . . . . . . . . . . . 103
6.4. Operating Mode Register . . . . . . . . . . 104
6.5. Register Descriptions . . . . . . . . . . . . . 105
6.6. Clock Generation Overview . . . . . . . . . 118
6.7. Power Down Modes Overview . . . . . . . 118
6.8. Stop and Wait Mode Disable Function . 119
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . 120
Part 12: Design Considerations . . . . . . . . 161
12.1. Thermal Design Considerations . . . . . 161
12.2. Electrical Design Considerations . . . . 162
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . 163
Part 13: Ordering Information . . . . . . . . . . 163
Part 7: Security Features . . . . . . . . . . . . . . 120
7.1. Operation with Security Enabled . . . . . 121
7.2. Flash Access Blocking Mechanisms . . 121
56F8355 Technical Data, Rev. 12
4
Freescale Semiconductor
Preliminary
56F8355/56F8155 Features
Part 1 Overview
1.1 56F8355/56F8155 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Core
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8355 and 56F8155 devices.
Table 1-1 Device Differences
Feature
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
56F8355
60MHz/60 MIPS
4KB
8KB
2x6
1
4
2x4
1
56F8155
40MHz/40MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
56F8355 Technical Data, Rev. 12
Freescale Semiconductor
Preliminary
5
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