Document Revision History
Version History
Rev 1.0
Rev 2.0
Initial Public Release
Added Package Pins to GPIO Table in
Part 8 General Purpose Input/Output (GPIO).
Added
“Typical Min” values to
Table 10-17.
Editing grammar, spelling, consistency of language throughout
family. Updated values in Regulator Parameters
Table 10-9;
External Clock Operation Timing
Requirements
Table 10-13;
SPI Timing
Table 10-18;
ADC Parameters
Table 10-24;
and IO Loading
Coefficients at 10MHz
Table 10-25.
Corrected
Table 4-6
Data Memory Map - changed address X:$FF0000 to X:$FFFF00
Added
Part 4.8,
added the word “access” to FM Error Interrupt in
Table 4-5,
documenting only Typ.
numbers for LVI in
Table 10-6,
updated EMI numbers and write-up in
Part 10.8.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data. Corrected typo in
Table 10-3
in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Module; removed references to JTAG pin
DE; corrected pin number for D14 in
Table 2-2;
added note to V
CAP
pin in
Table 2-2;
corrected
thermal numbers for 160 LQFP in
Table 10-3;
removed unneccessary notes in
Table 10-12;
corrected
temperature range in
Table 10-14;
added ADC calibration information to
Table 10-24
and new graphs
in
Figure 10-22.
Adding/clarifing notes to
Table 4-4
to help clarify independent program flash blocks and other
Program Flash modes, clarification in
Table 10-23,
corrected Digital Input Current Low (pull-up
enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Added 56F8157 information; edited to indicate differences in 56F8357 and 56F8157. Reformatted for
Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of elec-
trical tables for consistency throughout the family. Clarified I/O power description in
Table 2-2,
added
note to
Table 10-7
and clarified
Section 12.3.
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be determined by
reliability engineering. Clarified value and unit measure for Maximum allowed P
D
in
Table 10-3.
Cor-
rected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant
orderable part numbers in
Table 13-1.
Added 160MAPBGA information,TA equation updated in
Table 10-4
and additional minor edits
throughout data sheet
Updated
Table 10-24
to reflect new value for maximum Uncalibrated Gain Error
Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating
Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back
cover.
Corrected
Section 6.4
title (from Operation Mode Register to Operating Mode Register). Added
information/corrected state during reset in
Table 2-2.
Clarified external reference crystal frequency for
PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
Description of Change
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev 11.0
Rev. 12.0
Rev. 13.0
Rev. 14.0
56F8357 Technical Data, Rev. 15
2
Freescale Semiconductor
Preliminary
56F8357/56F8157 General Description
Note:
Features in italics are NOT available in the 56F8157 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB of
data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
RSTO
EMI_MODE
EXTBOOT
5
JTAG/
EOnCE
Port
OCR_DIS
V
DD
V
SS
7
6
Digital Reg
* Configuration
shown for on-chip
2.5V regulator
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package and
160MAPBGA
V
PP
2
V
CAP
4
V
DDA
2
V
SSA
RESET
6
3
4
6
3
4
4
4
5
4
4
PWM Outputs
PWMA
Analog Reg
Current Sense Inputs or
GPIOC
Fault Inputs
PWM Outputs
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Current Sense Inputs or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
AD1
TEMP_SENSE
Quadrature
Decoder 0 or
Quad
Timer or /
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
8K x 16
Boot Flash
R/W Control
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
External
Address Bus
Switch
6
2
8
4
1
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
External Bus
Interface Unit
System Bus
Control
4
Data Memory
4K x 16 Flash
8K x 16 RAM
3
7
9
External Data
Bus Switch
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
Bus Control
6
2
Decoding
Peripherals
Clock
resets
PLL
4
2
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
IRQA
IRQB
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
CLKO
CLKMODE
56F8357/56F8157 Block Diagram
56F8357 Technical Data, Rev. 15
4
Freescale Semiconductor
Preliminary
Table of Contents
Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 6
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8357/56F8157 Features . . . . . . . . . . . . . 6
Device Description . . . . . . . . . . . . . . . . . . . . 8
Award-Winning Development Environmen . 10
Architecture Block Diagram . . . . . . . . . . . . . 11
Product Documentation . . . . . . . . . . . . . . . 15
Data Sheet Conventions . . . . . . . . . . . . . . 15
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 126
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 126
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 126
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 126
Part 9: Joint Test Action Group (JTAG) . . 131
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 131
Part 2: Signal/Connection Descriptions . . . 16
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part 10: Specifications . . . . . . . . . . . . . . . 131
10.1. General Characteristics. . . . . . . . . . . . . . 131
10.2. DC Electrical Characteristics. . . . . . . . . . 135
10.3. AC Electrical Characteristics . . . . . . . . . . 139
10.4. Flash Memory Characteristics . . . . . . . . . 139
10.5. External Clock Operation Timing . . . . . . 140
10.6. Phase Locked Loop Timing. . . . . . . . . . . 140
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 141
10.8. External Memory Interface Timing . . . . . 141
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 144
10.10. Serial Peripheral Interface (SPI) Timing . 146
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 150
10.12. Quadrature Decoder Timing . . . . . . . . . . 150
10.13. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . 151
10.14. Controller Area Network (CAN) Timing . 152
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 152
10.16. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . 154
10.17. Equivalent Circuit for ADC Inputs . . . . . 157
10.18. Power Consumption . . . . . . . . . . . . . . . 157
Part 3: On-Chip Clock Synthesis (OCCS) . 39
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2. External Clock Operation . . . . . . . . . . . . . . 39
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 41
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers . . . .
Factory Programmed Memory. . . . . . . . . . .
41
42
43
46
47
48
49
76
Part 5: Interrupt Controller (ITCN) . . . . . . . . 76
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 76
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Functional Description . . . . . . . . . . . . . . . . . 76
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 78
Operating Modes . . . . . . . . . . . . . . . . . . . . . 78
Register Descriptions . . . . . . . . . . . . . . . . . 79
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Part 11: Packaging . . . . . . . . . . . . . . . . . . 159
11.1. 56F8357 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 159
11.2. 56F8157 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 166
Part 6: System Integration Module (SIM) . 106
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . .
Operating Mode Register . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . .
Clock Generation Overview . . . . . . . . . . .
Power Down Modes Overview . . . . . . . . .
Stop and Wait Mode Disable Function . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
106
107
107
108
121
121
122
123
Part 12: Design Considerations . . . . . . . . 170
12.1. Thermal Design Considerations . . . . . . . 170
12.2. Electrical Design Considerations . . . . . . 171
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . 172
Part 13: Ordering Information . . . . . . . . . 173
Part 7: Security Features . . . . . . . . . . . . . . 123
7.1. Operation with Security Enabled . . . . . . . 123
7.2. Flash Access Blocking Mechanisms . . . . 124
56F8357 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
5
FPGA/CPLD
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