Document Revision History
Version History
Rev. 0
Rev. 1
Initial Release
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference
crystal frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
Revised
Table 4-4
to include correct program Flash size.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a
debugging environment, TRST may be tied to V
SS
through a 1K resistor.
Description of Change
Rev. 2
Rev. 3
Rev. 4
Rev. 5
Please see http://www.freescale.com for the most current data sheet revision.
56F8335 Technical Data, Rev. 5
2
Freescale Semiconductor
Preliminary
56F8335/56F8135 General Description
Note:
Features in italics are NOT available in the 56F8135 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 64KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
•
Up to two
Quadrature Decoders
•
FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
RSTO
RESET
6
PWM Outputs
3
4
Current Sense Inputs
or
GPIOC
Fault Inputs
Program Controller
and Hardware
Looping Unit
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
6
PWM Outputs
3
4
4
4
5
4
4
Current Sense Inputs
or GPIOD
Fault Inputs
PWMB
Address
Generation Unit
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
AD1
VREF
PAB
PDB
CDBR
CDBW
ADCA
Memory
Program Memory
32K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
PDB
CDBR
CDBW
R/W Control
AD0
ADCB
AD1
TEMP_SENSE
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
Quad Timer
D or
GPIOE
FlexCAN
System Bus
Control
External Bus
Interface Unit
PAB
*
External
Address Bus
Switch
*
External
Data
Bus Switch
*
Bus
Control
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
4
D7-10 or GPIOF0-3
6
GPIOD0-5 or CS2-7
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
2
4
2
Decoding
Peripherals
RW
Control
IPAB
IPWDB
IPRDB
Clock
resets
P
System
O
Integration
R
Module
PLL
*
EMI not functional in
this package; use as
GPIO pins
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Interrupt
Watchdog Controller
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA IRQB
CLKO
CLKMODE
56F8335/56F8135 Block Diagram - 128 LQFP
56F8335 Technical Data, Rev. 5
Freescale Semiconductor
Preliminary
3
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8335/56F8135 Features . . . . . . . . . . . . . . .5
Device Description . . . . . . . . . . . . . . . . . . . . . 7
Award-Winning Development Environment . . .9
Architecture Block Diagram . . . . . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . . . . . 12
Data Sheet Conventions . . . . . . . . . . . . . . . . 13
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 120
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 120
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 120
Part 9: Joint Test Action Group (JTAG) . . 125
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 125
Part 2: Signal/Connection Descriptions . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part 10: Specifications. . . . . . . . . . . . . . . . 126
10.1. General Characteristics. . . . . . . . . . . . . . . 126
10.2. DC Electrical Characteristics. . . . . . . . . . . 130
10.3. AC Electrical Characteristics . . . . . . . . . . . 134
10.4. Flash Memory Characteristics . . . . . . . . . . 134
10.5. External Clock Operation Timing . . . . . . . 135
10.6. Phase Locked Loop Timing. . . . . . . . . . . . 135
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . . 136
10.8. Reset, Stop, Wait, Mode Select
and Interrupt Timing . . . . . . . . . . . 136
10.9. Serial Peripheral Interface (SPI) Timing . . . 138
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . . 142
10.11. Quadrature Decoder Timing . . . . . . . . . . . 142
10.12. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . . 143
10.13. Controller Area Network (CAN) Timing . . 144
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 144
10.15. Analog-to-Digital Converter (
ADC) Parameters . . . . . . . . . . . . . 146
10.16. Equivalent Circuit for ADC Inputs . . . . . . 148
10.17. Power Consumption . . . . . . . . . . . . . . . . 149
Part 3: On-Chip Clock Synthesis (OCCS) . 33
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2. External Clock Operation . . . . . . . . . . . . . . . 33
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 35
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Program Map. . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Vector Table . . . . . . . . . . . . . . . . . . .37
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Flash Memory Map . . . . . . . . . . . . . . . . . . . . 42
EOnCE Memory Map . . . . . . . . . . . . . . . . . . .43
Peripheral Memory Mapped Registers . . . . . .44
Factory Programmed Memory. . . . . . . . . . . . 71
Part 5: Interrupt Controller (ITCN) . . . . . . . . 71
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Functional Description . . . . . . . . . . . . . . . . . . 71
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 73
Operating Modes . . . . . . . . . . . . . . . . . . . . . . 73
Register Descriptions . . . . . . . . . . . . . . . . . . .74
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Part 11: Packaging . . . . . . . . . . . . . . . . . . 152
11.1. 56F8335 Package and
Pin-Out Information . . . . . . . . . . . . 152
11.2. 56F8135 Package and
Pin-Out Information . . . . . . . . . . . . 155
Part 6: System Integration Module (SIM) . 100
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . .
Operating Mode Register . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . . .
Clock Generation Overview. . . . . . . . . . . . .
Power-Down Modes Overview . . . . . . . . . .
Stop and Wait Mode Disable Function . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
100
101
101
102
114
115
116
116
Part 12: Design Considerations . . . . . . . . 159
12.1. Thermal Design Considerations . . . . . . . . . 159
12.2. Electrical Design Considerations . . . . . . . 159
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . . 159
Part 13: Ordering Information . . . . . . . . . . 159
Part 7: Security Features . . . . . . . . . . . . . 117
7.1. Operation with Security Enabled . . . . . . . . .117
7.2. Flash Access Blocking Mechanisms . . . . . .117
56F8335 Technical Data, Rev. 5
4
Freescale Semiconductor
Preliminary
56F8335/56F8135 Features
Part 1 Overview
1.1 56F8335/56F8135 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Core
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8335 and 56F8135 devices.
Table 1-1 Device Differences
Feature
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
56F8335
60MHz/60 MIPS
4KB
8KB
2x6
1
4
2x4
1
56F8135
40MHz/40MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
56F8335 Technical Data, Rev. 5
Freescale Semiconductor
Preliminary
5
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