Freescale Semiconductor
Advance Information
Document Number: MC33883
Rev 9.0, 1/2007
H-Bridge Gate Driver IC
The 33883 is an H-bridge gate driver (also known as a full-bridge
pre-driver) IC with integrated charge pump and independent high-
and low-side gate driver channels. The gate driver channels are
independently controlled by four separate input terminals, thus
allowing the device to be optionally configured as two independent
high-side gate drivers and two independent low-side gate drivers.
The low-side channels are referenced to ground. The high-side
channels are floating.
The gate driver outputs can source and sink up to 1.0 A peak
current pulses, permitting large gate-charge MOSFETs to be driven
and/or high Pulse Width Modulation (PWM) frequencies to be utilized.
A linear regulator is incorporated, providing a 15 V typical gate supply
to the low-side gate drivers.
Features
•
•
•
•
•
•
•
•
•
•
V
CC
Operating Voltage Range from 5.5 V up to 55 V
V
CC2
Operating Voltage Range from 5.5 V up to 28 V
CMOS / LSTTL Compatible I / O
1.0 A Peak Gate Driver Current
Built-In High-Side Charge Pump
Undervoltage Lockout (UVLO)
Overvoltage Lockout (OVLO)
Global Enable with <10
µA
Sleep Mode
Supports PWM up to 100 kHz
Pb-Free Packaging Designated by Suffix Code EG
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42343B
20-TERMINAL SOICW
33883
H-BRIDGE GATE DRIVER IC
ORDERING INFORMATION
Device
MC33883DW/R2
- 40°C to 125°C
MCZ33883EG/R2
20 SOICW
Temperature
Range (T
A
)
Package
VBAT VBOOST
33883
VCC
VCC2
G_EN
C1
C2
MCU
CP_OUT
LR_OUT
GATE_HS1
SRC_HS1
GATE_LS1
GATE_HS2
SRC_HS2
IN_HS1
GATE_LS2
IN_LS1
IN_HS2
/2
IN_LS2 GND_A GND
DC
Motor
Figure 1. 33883 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C1
V
CC,
V
CC2
Undervolt-
age/Over-
voltage
V
CC
V
CC
V
DD
EN
GND
G_EN
GND2
V
CC2
C2
V
CC2
C1
Charge
Pump
C2
V
POS
CP_OUT
V
DD
+5.0 V
EN Linear
GND Reg +14.5 V LR_OUT
V
CC2
V
CC
VCC2
VCC
CP_OUT
LR_OUT
GND_A
GND2
HIGH- AND LOW-SIDE
CONTROL WITH CHARGE PUMP
BRG_EN
IN_HS1
T
SD
1
V
CC
CP_OUT
OU
Con-
trol and
Logic
V
DD
/ V
POS
Level Shift
Pulse
Generator
IN
Output
Driver
GATE_HS
SRC_HS1
HIGH-SIDE CHANNEL
BRG_EN
IN_LS1
T
SD
1
T
SD
1
Thermal Shutdown
Con-
trol and
Logic
LR_OUT
V
DD
/ V
CC
Level Shift
Pulse
Generator
IN
Output
Driver
OU
GATE_LS1
LOW-SIDE CHANNEL
GND1
BRG_EN
IN_HS2
T
SD
2
V
CC
CP_OUT
OU
Con-
trol and
Logic
V
DD
/ V
POS
Level Shift
Pulse
Generator
IN
Output
Driver
GATE_HS
SRC_HS2
HIGH-SIDE CHANNEL
BRG_EN
IN_LS2
T
SD
2
T
SD
2
Thermal Shutdown
Con-
trol and
Logic
LR_OUT
V
DD
/ V
CC
Level Shift
Pulse
Generator
IN
Output
Driver
OU
GATE_LS2
LOW-SIDE CHANNEL
GND2
GND
GND
GND_
Figure 2. 33883 Simplified Internal Block Diagram
33883
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
G_EN
SRC_HS2
GATE_HS2
IN_HS2
IN_LS2
GATE_LS2
GND2
C1
GND_A
VCC2
C2
CP_OUT
SRC_HS1
GATE_HS1
IN_HS1
IN_LS1
GATE_LS1
GND1
LR_OUT
Figure 3. 33883 20-SOICW Terminal Connections
Table 1. 20-SOICW Terminal Definitions
A functional description of each terminal can be found in the
FUNCTIONAL TERMINAL DESCRIPTION
section beginning on
page 10.
Terminal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Terminal
Name
VCC
C2
CP_OUT
SRC_HS1
GATE_HS
1
IN_HS1
IN_LS1
Formal Name
Supply Voltage 1
Charge Pump Capacitor
Charge Pump Out
Source 1 Output High Side
Gate 1 Output High Side
Input High Side 1
Input Low Side 1
Device power supply 1.
External capacitor for internal charge pump.
External reservoir capacitor for internal charge pump.
Source of high-side 1 MOSFET
Gate of high-side 1 MOSFET.
Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH).
Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH).
Gate of low-side 1 MOSFET.
Device ground 1.
Output of internal linear regulator.
Device power supply 2.
Device analog ground.
External capacitor for internal charge pump.
Device ground 2.
Gate of low-side 2 MOSFET.
Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH).
Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH).
Gate of high-side 2 MOSFET.
Source of high-side 2 MOSFET.
Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN
logic LOW = Sleep Mode).
Definition
GATE_LS1 Gate 1 Output Low Side
GND1
LR_OUT
VCC2
GND_A
C1
GND2
Ground 1
Linear Regulator Output
Supply Voltage 2
Analog Ground
Charge Pump Capacitor
Ground 2
GATE_LS2 Gate 2 Output Low Side
IN_LS2
IN_HS2
GATE_HS
2
SRC_HS2
G_EN
Input Low Side 2
Input High Side 2
Gate 2 Output High Side
Source 2 Output High Side
Global Enable
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
ELECTRICAL RATINGS
Supply Voltage 1
Supply Voltage 2
(1)
Linear Regulator Output Voltage
High-Side Floating Supply Absolute Voltage
High-Side Floating Source Voltage
High-Side Source Current from CP_OUT in Switch ON State
High-Side Gate Voltage
High-Side Gate Source Voltage
(2)
V
CC
V
CC2
V
LR_OUT
V
CP_OUT
V
SRC_HS
I
S
V
GATE_HS
V
GATE_HS
-
V
SRC_HS
V
CP_OUT
-
V
GATE_HS
V
GATE_LS
V
G_EN
V
IN
V
C1
V
C2
-0.3 to 65
-0.3 to 35
-0.3 to 18
-0.3 to 65
-2.0 to 65
250
-0.3 to 65
-0.3 to 20
V
V
V
V
V
mA
V
V
Symbol
Value
Unit
High-Side Floating Supply Gate Voltage
-0.3 to 65
V
Low-Side Gate Voltage
Wake-Up Voltage
Logic Input Voltage
Charge Pump Capacitor Voltage
Charge Pump Capacitor Voltage
ESD Voltage
(3)
Human Body Model on All Pins (V
CC
and V
CC2
as Two Power
Supplies)
Machine Model
-0.3 to 17
-0.3 to 35
-0.3 to 10
-0.3 to V
LR_OUT
-0.3 to 65
V
V
V
V
V
V
V
ESD1
V
ESD2
±1500
±130
Notes
1. V
CC2
can sustain load dump pulse of 40 V, 400 ms, 2.0
Ω.
2. In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is
needed as shown in
Figure 14.
3. ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω).
33883
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ 25°C
Thermal Resistance (Junction to Ambient)
Operating Junction Temperature
Storage Temperature
Peak Package Reflow Temperature During Reflow
(4)
,
(5)
P
D
R
θJA
T
J
T
STG
T
PPRT
1.25
100
-40 to 150
-65 to 150
Note 5
W
°C / W
°C
°C
°C
Symbol
Value
Unit
Notes
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33883
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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