Freescale Semiconductor
Technical Data
Document Number: MC34702
Rev 6.0, 2/2007
3.0 A Switch-Mode Power
Supply with Linear Regulator
The 34702 provides the means to efficiently supply the Freescale
Power QUICC™ I, II, and other families of Freescale
microprocessors and DSPs. The 34702 incorporates a high-
performance switching regulator, providing the direct supply for the
microprocessor’s core, and a low dropout (LDO) linear regulator
control circuit providing the microprocessor I/O and bus voltage.
The switching regulator is a high-efficiency synchronous buck
regulator with integrated N-channel power MOSFETs to provide
protection features and to allow space-efficient, compact design.
The 34702 incorporates many advanced features; e.g., precisely
maintained up/down power sequencing, ensuring the proper
operation and protection of the CPU and power system.
Features
•
•
•
•
•
•
•
•
•
Operating Voltage from 2.8 V to 6.0 V
High-Accuracy Output Voltages
Fast Transient Response
Switcher Output Current Up to 3.0 A
Undervoltage Lockout and Overcurrent Protection
Enable Inputs and Programmable Watchdog Timer
Voltage Margining via I
2
C™ Bus
Reset with Programmable Power-ON Delay
Pb-Free Packaging Designated by Suffix Code EK
I
2
C is a trademark of Philips Corporation.
34702
POWER SUPPLY
INTEGRATED CIRCUIT
EK (PB-FREE) SUFFIX
98AARH99137A
32-PIN SOICW
ORDERING INFORMATION
Device
MC34702EK/R2
Temperature
Range (T
A
)
-40 to 85°C
Package
32 SOICW
2.8 V to 6.0 V Input
34702
VIN2
VBD
VBST
RT
VIN1
LDRV
CS
LDO
LFB
MPC8xxx
RST
BOOT
SW
VOUT
PGND
INV
VDDI
VBST
Adjustable:
0.8 V to VIN -
Dropout
PORESET
Other
Circuits
Adjustable:
0.8 V to VIN -
Dropout
VDDH (I/Os)
ADDR
SDA
SCL
GND
EN1
EN2
CLKSYN
CLKSEL
Optional
FREQ
VDDL (Core)
Figure 1. 34702 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIN1
VIN
VDDI
Internal
Supply
8.0 V
VDDI
VDDI
VBST
Power
Enable
VDDI
Bandgap
Voltage
Reference
VDDI
VLDO
Power
Sequencing
Reset
Q6
Reset
Control
POR
Timer
SysCon
INV
LFB
I
2
C
Control
Voltage Margining
VOUT
Watchdog Timer
Current Limit
VDDI
Buck
HS
and
LS
Driver
Q1
VIN2
(2)
VBST
BOOT
Power
Down
Power
Seq
UVLO
Q4
VDDI
Linear
Regulator
Control
ILim
LFB
LCMP
To Reset
Control
LDRV
CS
VBST
VBST
VBD
Q5
Boost
Control
VREF
VREF
EN1
EN2
RST
RT
Control
I
2
C
Thermal
Limit
ADDR
SDA
SCL
Switcher
Oscillator
300 kHz
Ramp
Gen.
I
2
C
Interface
PWM
Comp
Error
Amp
CLKSEL
CLKSYN FREQ
Figure 2. 34702 Simplified Internal Block Diagram
34702
2
+
VREF
-
LDO
VREF
VBST
SysCon
SoftSt
Buck
Control
Logic
SW
(2)
Q2
PGND
(2)
+
+
0.8 V
To Reset
Control
INV
VOUT
VOUT
Q3
-
-
Power
Seq
GND (4)
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
FREQ
INV
V
OUT
V
IN2
V
IN2
SW
SW
GND
GND
PGND
PGND
VBD
VBST
BOOT
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CLKSYN
CLKSEL
RST
RT
EN2
EN1
ADDR
GND
GND
V
DD1
V
IN1
LDRV
CS
LDO
LFB
LCMP
Figure 3. Pin Connections
Table 1.
Pin Function Description
A functional description of each pin can be found in the
Functional Pin Description
section beginning on
page 16.
Pin
1
Pin Name
FREQ
Formal Name
Oscillator Frequency
Definition
This switcher frequency selection pin can be adjusted by connecting external
resistor R
F
to the FREQ pin. The default switching frequency (FREQ pin left open or
tied to V
DDI
) is set to 300 kHz.
Buck Controller Error Amplifier inverting input.
Output voltage of the buck converter. Input pin of the switching regulator power
sequence control circuit.
Buck regulator power input. Drain of the high-side power MOSFET.
Buck regulator switching node. This pin is connected to the inductor.
Analog ground of the IC, thermal heatsinking.
2
3
INV
VOUT
Inverting Input
Output Voltage
4, 5
6, 7
8, 9
24, 25
10, 11
12
13
VIN2
SW
GND
Input Voltage 2
Switch
Ground
PGND
VBD
VBST
Power Ground
Boost Drain
Boost Voltage
Buck regulator power ground.
Drain of the internal boost regulator power MOSFET.
Internal boost regulator output voltage. The internal boost regulator provides a
20 mA output current to supply the drive circuits for the integrated power MOSFETs
and the external N-channel power MOSFET of the linear regulator. The voltage at
the V
BST
pin is 7.75V nominal.
Bootstrap capacitor input.
I
2
C bus pin. Serial data.
I
2
C bus pin. Serial clock.
Linear regulator compensation pin.
Linear regulator feedback pin.
Input pin of the linear regulator power sequence control circuit.
14
15
16
17
18
19
BOOT
SDA
SCL
LCMP
LFB
LDO
Bootstrap
Serial Data
Serial Clock
Linear Compensation
Linear Feedback
Linear Regulator
34702
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1.
Pin Function Description (continued)
A functional description of each pin can be found in the
Functional Pin Description
section beginning on
page 16.
Pin
20
Pin Name
CS
Formal Name
Current Sense
Definition
Current sense pin of the LDO. Overcurrent protection of the linear regulator external
power MOSFET. The voltage drop over the LDO current sense resistor R
S
is sensed
between the CS and LDO pins. The LDO current limit can be adjusted by selecting
the proper value of the current sensing resistor R
S
.
LDO gate drive of the external pass N-channel MOSFET.
The input supply pin for the integrated circuit. The internal circuits of the IC are
supplied through this pin.
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is
recommended.
I
2
C address selection. This pin can either be left open, tied to V
DDI
, or grounded
through a 10 kΩ resistor.
Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2
inputs determines operation mode and type of power sequencing of the IC.
Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2
inputs determines operation mode and type of power sequencing of the IC.
This pin allows programming of the Power-ON Reset delay by means of an external
RC network.
The Reset Control circuit monitors both the switching regulator and the LDO
feedback voltages. It is an open drain output and has to be pulled up to some supply
voltage (e.g., the output of the LDO) by an external resistor.
This pin sets the CLKSYN pin as either an oscillator output or a synchronization input
pin. The CLKSEL pin is also used for the I
2
C address selection.
Oscillator output/synchronization input pin.
21
22
LDRV
VIN1
Linear Drive
Input Voltage 1
23
VDDI
Power Supply
26
ADDR
Address
27
EN1
Enable 1
28
EN2
Enable 2
29
RT
Reset Timer
30
RST
Reset Output
(Active LOW)
31
CLKSEL
Clock Selection
32
CLKSYN
Clock Synchronization
34702
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Rating
ELECTRICAL RATINGS
Supply Voltage
Switching Node Voltage
Buck Regulator Bootstrap Input Voltage (BOOT - SW)
Boost Regulator Output Voltage
Boost Regulator Drain Voltage
RST
Drain Voltage
Symbol
Value
Unit
V
IN1
, V
IN2
V
SW
V
IN(BOOT)
V
BST
V
BD
V
RST
-0.3 to 7.0
-1.0 to 7.0
-0.3 to 8.5
-0.3 to 8.5
-0.3 to 9.5
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 7.0
V
V
V
V
V
V
V
V
V
Enable Pin Voltage at EN1, EN2
Logic Pin Voltage at SDA, SCL
Analog Pin Voltage
LDO, VOUT,
RST
LDRV, LCMP, CS
Pin Voltage at CLKSEL, ADDR, RT, FREQ, VDDI, CLKSYN, INV, LFB
ESD Voltage
(1)
Human Body Model
Machine Model
V
EN
V
LOG
V
OUT
V
LIN
V
LOGIC
-0.3 to 7.0
-0.3 to 8.5
-0.3 to 3.6
V
V
V
ESD
±2000
±200
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω),
and the Charge Device Model.
34702
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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