256MB, 512MB, 1GB Unbuffered SODIMM
Preliminary
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb D-die
66 TSOP-II & 54 sTSOP-II with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
Table of Contents
Preliminary
DDR SDRAM
1.0 Ordering Information................................................................................................................... 4
2.0 Operating Frequencies................................................................................................................ 4
3.0 Feature.......................................................................................................................................... 4
4.0 Pin Configuration (Front side/back side) ................................................................................. 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Functional Block Diagram .......................................................................................................... 6
6.1 256MB, 32M x 64 Non ECC Module (M470L3324DU0)
........................................................................ 6
6.2 512MB, 64M x 64 Non ECC Module (M470L6524DU0).......................................................................................
7
6.3 1GB, 128M x 64 Non ECC Module (M470L2923DV0)
.......................................................................... 8
7.0 Absolute Maximum Ratings........................................................................................................ 9
8.0 DC Operating Conditions............................................................................................................ 9
9.0 DDR SDRAM IDD spec table ..................................................................................................... 10
9.1 M470L3324DU0 [ (32M x 16) * 4, 256MB Non ECC Module ]
..................................................................................
10
9.2 M470L6524DU0 [ (32M x 16) * 8, 512MB Non ECC Module ]
..................................................................................
10
9.3 M470L2923DV0 [ (64M x 8) * 16, 1GB Non ECC Module ]
.......................................................................................
11
10.0 AC Operating Conditions........................................................................................................ 12
11.0 Input/Output Capacitance ....................................................................................................... 12
12.0 AC Timming Parameters & Specifications ............................................................................ 13
13.0 System Characteristics for DDR SDRAM .............................................................................. 14
14.0 Component Notes.................................................................................................................... 15
15.0 System Notes ........................................................................................................................... 16
16.0 Command Truth Table............................................................................................................. 17
17.0 Physical Dimensions............................................................................................................... 18
17.1 32Mx64 (M470L3324DU0)
......................................................................................................... 18
17.2 64Mx64 (M470L6524DU0)
......................................................................................................... 19
17.3 128Mx64 (M470L2923DV0)
....................................................................................................... 20
Rev. 0.1 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
Revision History
Revision
0.0
0.2
Month
April
June
Year
2005
2005
- First version for internal review
- Changed master format.
History
Preliminary
DDR SDRAM
Rev. 0.1 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
Preliminary
DDR SDRAM
200Pin Unbuffered SODIMM based on 512Mb D-die (x8, x16)
1.0 Ordering Information
Part Number
M470L3324DU0-C(L)CC/B3/A2/B0
M470L6524DU0-C(L)CC/B3/A2/B0
M470L2923DV0-C(L)CC/B3/A2/B0
Density
256MB
512MB
1GB
Organization
32M x 64
64M x 64
128M x 64
Component Composition
32Mx16 (K4H511638D) * 4EA
32Mx16 (K4H511638D) * 8EA
64Mx8 (K4H510838D) * 16EA
Height
1,250mil
1,250mil
1,250mil
2.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height - 256MB(non ECC/ECC SS, 1250mil), 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil)
• SSTL_2 Interface
• 66pin TSOP II & 54pin sTSOP II
Pb-Free
package
•
RoHS compliant
Rev. 0.1 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
4.0 Pin Configuration (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
KEY
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
Pin
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
Front
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2
VDD
CKE1
DU
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE
CS0
*DU(A13)
VSS
DQ32
DQ33
VDD
DQS4
Pin
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
42
44
46
48
50
52
54
56
58
60
62
64
66
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Back
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
KEY
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Pin
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
Back
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
Preliminary
DDR SDRAM
Pin
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
*DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
*DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS
CAS
CS1
DU
VSS
DQ36
DQ37
VDD
DM4
Note :
1. * : These pins are not used in this module.
2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64(M470~ ) module, & used on x72(M485 ~ ) module.
3. Pins 95,122 are NC for 1Row module & used for 2Row moule(M470L6524DU0).
5.0 Pin Description
Pin Name
A0 ~ A12
BA0 ~ BA1A
DQ0 ~ DQ63
DQS0 ~ DQS8
CK0,CK0 ~ CK2, CK2
CKE0, CKE1(for double banks)
CS0, CS1(for double banks)
RAS
CAS
WE
CB0 ~ CB7(for x72 module)
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Check bit(Data-in/data-out)
Pin Name
DM0 ~7,8(for ECC) Data - in mask
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
Power supply
(2.5V for DDR266/333, 2.6V for DDR400)
Power Supply for DQS
(2.5V for DDR266/333, 2.6V for DDR400)
Ground
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
Serial clock
Address in EEPROM
VDD, VDDQ level detection
No connection
Function
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
Rev. 0.1 June 2005
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