Freescale Semiconductor
Data Sheet: Advance Information
MCF5208EC
Rev. 1, 4/2007
MCF5208
Microprocessor Data Sheet
Supports MCF5207 & MCF5208
by: Microcontroller Division
®
ColdFire
The MCF5207 and MCF5208 devices are
highly-integrated, 32-bit microprocessors based on the
version 2 ColdFire microarchitecture. Both devices
contain a 16-Kbyte internal SRAM, an 8-Kbyte
configurable cache, a 2-bank SDR/DDR SDRAM
controller, a 16-channel DMA controller, up to three
UARTs, a queued SPI, a low-power management
modeule, and other peripherals that enable the MCF5207
and MCF5208 for use in industrial control and
connectivity applications. The MCF5208 device also
features a 10/100 Mbps fast ethernet controller.
This document provides detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications of the MCF5207 and MCF5208
microprocessors. It was written from the perspective of
the MCF5208 device. See the following section for a
summary of differences between the two devices.
Table of Contents
1
2
3
4
5
6
MCF5207/8 Device Configurations......................2
Ordering Information ...........................................2
Signal Descriptions..............................................3
Mechanicals and Pinouts ....................................8
Electrical Characteristics ...................................17
Revision History ................................................44
© Freescale Semiconductor, Inc., 2007. All rights reserved.
MCF5207/8 Device Configurations
1
MCF5207/8 Device Configurations
Table 1. MCF5207 & MCF5208 Configurations
Module
Version 2 ColdFire Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock
Peripheral and External Bus Clock
(Core clock
÷ 2)
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
SDR/DDR SDRAM Controller
Fast Ethernet Controller (FEC)
Low-Power Management Module
UARTs
I
2
C
QSPI
32-bit DMA Timers
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
FlexBus External Interface
General Purpose I/O Module (GPIO)
JTAG - IEEE
®
1149.1 Test Access Port
Package
•
—
•
3
•
•
4
•
4
•
1
•
•
•
•
144 LQFP
144 MAPBGA
MCF5207
•
MCF5208
•
The following table compares the two devices described in this document:
up to 166.67 MHz
up to 83.33 MHz
up to 159
8 Kbytes
16 Kbytes
•
•
•
3
•
•
4
•
4
•
1
•
•
•
•
160 QFP
196 MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
MCF5207CAG166
MCF5207CVM166
MCF5208CAB166
MCF5208CVM166
Description
MCF5207 RISC Microprocessor, 144 LQFP
MCF5207 RISC Microprocessor, 144 MAPBGA
MCF5208 RISC Microprocessor, 160 QFP
MCF5208 RISC Microprocessor, 196 MAPBGA
Speed
166.67 MHz
166.67 MHz
166.67 MHz
166.67 MHz
Temperature
–40
°
to
+85
°
C
–40
°
to
+85
°
C
–40
°
to
+85
°
C
–40
°
to
+85
°
C
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 1
2
Freescale Semiconductor
Signal Descriptions
3
Signal Descriptions
The following table lists all the MCF5208 pins grouped by function. The Dir column is the direction for
the primary function of the pin only. Refer to
Section 4, “Mechanicals and Pinouts”
for package diagrams.
For a more detailed discussion of the MCF5208 signals, consult the
MCF5208 Reference Manual
(MCF5208RM).
NOTE
In this table and throughout this document, a single signal within a group is
designated without square brackets (i.e., A23), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 3. MCF5207/8 Signal Information and Muxing
Voltage
Domain
Signal Name
GPIO
Alternate 1
Alternate 2
MCF5207
144
LQFP
MCF5207
144
MAPBGA
MCF5208
160
QFP
MCF5208
196
MAPBGA
Dir.
1
Reset
RESET
2
RSTOUT
—
—
—
—
—
—
I
O
Clock
EXTAL
XTAL
FB_CLK
—
—
—
—
—
—
—
—
—
I
O
O
EVDD
EVDD
SDVDD
EVDD
EVDD
82
74
J10
M12
90
82
J14
N14
78
80
34
K12
J12
L1
86
88
40
L14
K14
N1
Mode Selection
RCON
2
DRAMSEL
—
—
—
—
—
—
I
I
EVDD
EVDD
144
79
C4
H10
160
87
C3
K11
FlexBus
A[23:22]
A[21:16]
—
—
FB_CS[5:4]
—
—
—
O
O
SDVDD
SDVDD
118, 117
116–114,
112, 108,
107
106, 105
104–102
101
B9, A10
C9, A11,
B10, A12,
C11, B11
B12, C12
D11, E10,
D12
C10
126, 125
124, 123,
122, 120,
116, 115
114, 113
112, 111,
110
109
B11, A11
B12, A12,
A13, B13,
B14, C13
C14, D12
D13, D14,
E11
E12
A[15:14]
A[13:11]
A10
—
—
—
SD_BA[1:0]
3
SD_A[13:11]
3
—
—
—
—
O
O
O
SDVDD
SDVDD
SDVDD
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 1
Freescale Semiconductor
3
Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
Voltage
Domain
Signal Name
A[9:0]
GPIO
—
Alternate 1
SD_A[9:0]
3
Alternate 2
—
MCF5207
144
LQFP
100–91
MCF5207
144
MAPBGA
E11, D9,
E12, F10,
F11, E9,
F12, G10,
G12, F9
F1, F2, G1,
G2, G4, G3,
H1, H2, K3,
L2, L3, K2,
M3, J4, M4,
K4
B2, B1, C2,
C1, D2, D1,
E2, E1, L5,
K5, L6, J6,
M6, J7, L7,
K7
F4, L4, E3,
J5
J8
G11
K6
B3
MCF5208
160
QFP
108–99
MCF5208
196
MAPBGA
E13, E14,
F11–F14,
G11–G14
Dir.
1
O
I/O
SDVDD
D[31:16]
—
SD_D[31:16]
4
—
SDVDD
21–28,
40–47
27–34,
46–53
J4–J1,
K4–K1, M3,
N3, M4, N4,
P4, L5, M5,
N5
F3–F1,
G4–G1, H1,
N6, P6, L7,
M7, N7, P7,
N8, P8
H2, P5, H4,
M6
M8
H14
L8
E3
D[15:0]
—
FB_D[31:16]
4
—
I/O
SDVDD
8–15, 51–58
16–23,
57–64
BE/BWE[3:0]
OE
TA
2
R/W
TS
PBE[3:0]
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
SD_DQM[3:0]
3
—
—
—
DACK0
—
—
—
—
—
O
O
I
O
O
SDVDD
20, 48, 18,
50
60
90
59
4
26, 54, 24,
56
66
98
65
12
SDVDD
SDVDD
SDVDD
SDVDD
Chip Selects
FB_CS[3:2]
FB_CS1
FB_CS0
PCS[3:2]
PCS1
—
—
SD_CS1
—
—
—
—
O
O
O
SDVDD
SDVDD
SDVDD
119, 120
121
122
D7, A9
C8
B8
—
127
128
C11, A10
B10
C10
SDRAM Controller
SD_A10
SD_CKE
SD_CLK
SD_CLK
SD_CS0
SD_DQS[3:2]
SD_SCAS
SD_SRAS
SD_SDR_DQS
SD_WE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
37
6
31
32
7
19, 49
38
39
29
5
M1
C3
J1
K1
A1
F3, M5
M2
J2
H3
D3
43
14
37
38
15
25, 55
44
45
35
13
N2
E1
L1
M1
F4
H3, L6
P2
P3
L3
E2
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 1
4
Freescale Semiconductor
Signal Descriptions
Table 3. MCF5207/8 Signal Information and Muxing (continued)
Voltage
Domain
Signal Name
GPIO
Alternate 1
Alternate 2
MCF5207
144
LQFP
MCF5207
144
MAPBGA
MCF5208
160
QFP
MCF5208
196
MAPBGA
Dir.
1
I
I
I
FEC
FEC_MDC
FEC_MDIO
FEC_TXCLK
—
FEC_TXEN
FEC_TXD0
FEC_COL
FEC_RXCLK
FEC_RXDV
FEC_RXD0
FEC_CRS
FEC_TXD[3:1]
—
FEC_TXER
FEC_RXD[3:2]
—
FEC_RXD1
—
FEC_RXER
PFECI2C3
PFECI2C2
PFECH7
PFECH6
PFECH6
PFECH5
PFECH4
PFECH3
PFECH2
PFECH1
PFECH0
PFECL[7:5]
PFECL4
PFECL4
PFECL[3:2]
PFECL1
PFECL1
PFECL0
PFECL0
I2C_SCL
2
I2C_SDA
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U2TXD
U2RXD
—
U1RTS
U1RTS
—
—
—
—
—
—
—
U0RTS
U0RTS
—
U1CTS
U1CTS
U0CTS
U0CTS
O
I/O
I
O
O
O
I
I
I
I
I
O
O
O
I
I
I
I
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
External Interrupts Port
5
IRQ7
2
IRQ4
2
IRQ1
2
PIRQ7
2
PIRQ4
2
PIRQ1
2
—
DREQ0
2
—
—
—
—
EVDD
EVDD
EVDD
134
133
132
A5
C6
B6
142
141
140
C7
D7
D8
—
—
—
142
—
—
—
—
—
—
—
—
141
—
—
139
—
140
—
—
—
—
A2
—
—
—
—
—
—
—
—
D5
—
—
B4
—
E4
—
148
147
157
—
158
3
7
154
153
152
8
6–4
—
156
149–150
—
151
—
155
D6
C6
B3
—
A2
B1
D3
B4
A4
D5
D2
C1, C2, B2
—
A3
A5, B5
—
C5
—
C4
Note:
The MCF5207 does not contain an FEC module. However, the UART0 and UART1 control signals (as well as their GPIO signals)
are available by setting the appropriate FEC GPIO port registers.
I
2
C
I2C_SDA
2
I2C_SCL
2
PFECI2C0
2
PFECI2C1
2
U2RXD
2
U2TXD
2
—
—
I/O
I/O
DMA
DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing:
TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0.
EVDD
EVDD
—
—
—
—
—
—
D1
E4
MCF5208 ColdFire
®
Microprocessor Data Sheet, Rev. 1
Freescale Semiconductor
5