EEWORLDEEWORLDEEWORLD

Part Number

Search

74F32MTCX

Description
OR Gate, F/FAST Series, 4-Func, 2-Input, TTL, PDSO14, 4.40 MM, MO-153, TSSOP-14
Categorylogic    logic   
File Size77KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

74F32MTCX Overview

OR Gate, F/FAST Series, 4-Func, 2-Input, TTL, PDSO14, 4.40 MM, MO-153, TSSOP-14

74F32MTCX Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP14,.25
Contacts14
Reach Compliance Codeunknown
seriesF/FAST
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length5 mm
Logic integrated circuit typeOR GATE
MaximumI(ol)0.02 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)15.5 mA
Prop。Delay @ Nom-Sup6.6 ns
propagation delay (tpd)6.6 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
Base Number Matches1
74F32 Quad 2-Input OR Gate
April 1988
Revised August 2000
74F32
Quad 2-Input OR Gate
General Description
This device contains four independent gates, each of which
performs the logic OR function.
Ordering Code:
Order Number
74F32SC
74F32SJ
74F32MTC
74F32PC
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
U.L.
HIGH/LOW
1.0/1.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
0.6 mA
1 mA/20 mA
© 2000 Fairchild Semiconductor Corporation
DS009463
www.fairchildsemi.com

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1584  499  2287  2220  943  32  11  47  45  19 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号