• On-chip 4-deep read buffer supports burst or simple block
reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface can operate at half-processor frequency
R3081 BLOCK DIAGRAM
ClkIn
Clock Generator
Unit/Clock Doubler
Master Pipeline Control
System Control
Coprocessor
(CP0)
Exception/Control
Registers
Memory Management
Registers
Int(5:0)
BrCond(3:2,0)
Integer
CPU Core
General Registers
(32 x 32)
ALU
Shifter
Mult/Div Unit
Address Adder
PC Control
Virtual Address
FP Interrupt
Floating Point
Coprocessor
(CP1)
Register Unit
(16 x 64)
Exponent Unit
Add Unit
Divide Unit
Multiply Unit
Exception/Control
Translation
Lookaside Buffer
(64 entries)
Physical Address Bus
32
Data Bus
Configurable
Data
Cache
(4kB/8kB)
Configurable
Instruction
Cache
(16kB/8kB)
Data Bus
36
Parity
Generator
4-deep
Read
Buffer
R3051 Superset Bus Interface Unit
4-deep
Write
Buffer
DMA
Arbiter
BIU
Control
Coherency
Logic
Address/
Data
DMA
Ctrl
Rd/Wr
Ctrl
SysClk
Invalidate
Control
2889 drw 01
The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc.
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Microcontroller MCU
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