DC COMPONENTS CO., LTD.
R
DISCRETE SEMICONDUCTORS
DCR100-3
THRU
DCR100-8
TECHNICAL SPECIFICATIONS OF SENSITIVE GATE SILICON CONTROLLED RECTIFIERS
VOLTAGE RANGE - 100 to 600 Volts
CURRENT - 0.8 Ampere
Description
* Driven directly with IC and MOS device
* Feature proprietary, void-free glass passivated chips
* Available in voltage ratings from 100 to 600 volts
* Sensitive gate trigger current
* Designed for high volume, line-powered control
application in relay lamp drivers, small motor controls,
gate drivers for large thyristors
TO-92
.190(4.83)
.170(4.33)
.190(4.83)
.170(4.33)
2 Typ
o
o
Pinning
1 = Cathode, 2 = Gate, 3 = Anode
Absolute Maximum Ratings
(T
A
=25
o
C)
Characteristic
Peak Repetitive Off-State
Voltage and Reverse Voltage
DCR100-3
DCR100-4
DCR100-6
DCR100-8
Symbol
V
DRM
,
V
RRM
I
T(RMS)
I
TSM
I
GM
P
GM
P
G(AV)
V
GRM
T
J
T
STG
Rating
100
200
400
600
0.8
8
0.8
0.1
0.01
6.0
-40 to +110
-40 to +150
Unit
V
2 Typ
.500
Min
(12.70)
.022(0.56)
.014(0.36)
.100
Typ
(2.54)
.022(0.56)
.014(0.36)
On-State RMS Current
(T
A
=57
o
C, 180
o
Conduction Angles)
Peak Non-repetitive Surge Current
(1/2 Cycle, Sine Wave 60Hz)
Forward Peak Gate Current(For 3µ sec.)
Forward Peak Gate Power Dissipation
Forward Average Gate Power Dissipation
Reverse Peak Gate Voltage
Operating Junction Temperature
Storage Temperature
.050
Typ
(1.27)
A
A
A
W
W
V
o
o
3 2 1
.148(3.76)
.132(3.36)
.050
Typ
o
o
5 Typ 5 Typ (1.27)
C
Dimensions in inches and (millimeters)
C
Electrical Characteristics
o
Characteristic
Peak Repetitive Forward or Reverse
Off-State Blocking Current
Peak Forward On-State Voltage
Continuous DC Gate Trigger Current
Continuous DC Gate Trigger Voltage
DC Holding Current
(Ratings at 25 C ambient temperature unless otherwise specified)
Symbol
T
A
=25 C
T
A
=125 C
o
o
Min
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
5
2.2
75
Max
10
200
1.7
200
0.8
10
-
-
-
Unit
µA
V
µA
V
mA
V/µS
µsec
o
Test Conditions
V
AK
=Rated V
DRM
or V
RRM
R
GK
=1KΩ
I
TM
=0.8A Peak, T
C
=25
o
C
V
AK
=7V DC, R
L
=100Ω
V
AK
=7V DC, R
L
=100Ω
R
GK
=1KΩ, Gate Open
R
GK
=1KΩ, Gate Open
I
GT
=10mA
-
I
DRM
, I
RRM
V
TM
I
GT
V
GT
I
H
dv/dt
T
gt
R
θJC
Critical Rate-of-Rise of Off-State Voltage
Gate Controlled Turn-on Time(t
D
+t
R
)
Thermal Resistance, Junction to Case
C/W
FPGA/CPLD
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