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5962-8946804XX

Description
UV PLD, 42ns, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68
CategoryProgrammable logic devices    Programmable logic   
File Size618KB,17 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

5962-8946804XX Overview

UV PLD, 42ns, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68

5962-8946804XX Parametric

Parameter NameAttribute value
MakerCypress Semiconductor
Parts packaging codePGA
package instructionWPGA,
Contacts68
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Other featuresLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency40 MHz
JESD-30 codeS-CPGA-P68
JESD-609 codee0
length27.9527 mm
Dedicated input times7
Number of I/O lines52
Number of terminals68
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize7 DEDICATED INPUTS, 52 I/O
Output functionMACROCELL
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeWPGA
Package shapeSQUARE
Package formGRID ARRAY, WINDOW
Programmable logic typeUV PLD
propagation delay42 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width27.9527 mm
Base Number Matches1
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