Philips Semiconductors
Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
FEATURES
•
5 V tolerant inputs/outputs, for interfacing with 5 V logic
•
Supply voltage range from 1.2 to 3.6 V
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
High impedance when V
CC
= 0 V
•
Flow-through pin-out architecture
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
The 74LVC573A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 or 5 V environment.
QUICK REFERENCE DATA
SYMBOL
t
PHL
/t
PLH
Dn to Qn
LE to Qn
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per latch notes 1 and 2
PARAMETER
propagation delay
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
3.4
3.1
5.0
15
74LVC573A
The 74LVC573A is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus-oriented applications. A Latch Enable (LE)
input and an Output Enable (OE) input are common to all
internal latches.
The 74LVC573A consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition, the
latches are transparent, i.e. a latch output will change each
time its corresponding D-input changes. When LE is LOW,
the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW
transition of LE. When OE is LOW, the contents of the
eight latches are available at the outputs. When OE is
HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the
latches.
The 74LVC573A is functionally identical to the
74LVC373A, but the 74LVC373A has a different pin
arrangement.
TYPICAL
ns
ns
pF
pF
UNIT
2003 Oct 03
2
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
FUNCTION TABLE
See note 1.
INPUT
OPERATING MODES
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
Note
1. H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
ORDERING INFORMATION
TYPE NUMBER
74LVC573AD
74LVC573ADB
74LVC573APW
74LVC573ABQ
PINNING
PIN
1
2
3
4
5
6
7
8
9
SYMBOL
OE
D0
D1
D2
D3
D4
D5
D6
D7
DESCRIPTION
output enable input (active
LOW)
data input
data input
data input
data input
data input
data input
data input
data input
TEMPERATURE
RANGE
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PACKAGE
PINS
20
20
20
20
PIN
10
11
12
13
14
15
16
17
18
19
20
PACKAGE
SO20
SSOP20
TSSOP20
DHVQFN20
SYMBOL
GND
LE
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
V
CC
L
L
L
L
H
H
LE
H
H
L
L
L
L
Dn
L
H
l
h
l
h
74LVC573A
INTERNAL
LATCH
L
H
L
H
L
H
OUTPUT
Qn
L
H
L
H
Z
Z
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT163-1
SOT339-1
SOT360-1
SOT764-1
DESCRIPTION
ground (0 V)
latch enable input (active HIGH)
data output
data output
data output
data output
data output
data output
data output
data output
supply voltage
2003 Oct 03
3
Embedded System
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