ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
OCTOBER 2006
REV. 4.2.1
GENERAL DESCRIPTION
The ST16C2552 (2552) is a dual universal
asynchronous receiver and transmitter (UART). The
ST16C2552 is an improved version of the PC16552
UART. The 2552 provides enhanced UART functions
with 16 byte FIFOs, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and
operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Indepedendent
programmable baud rate generators are privded to
select transmit and receive clock rates from 50 Bps to
4 Mbps. The baud rate generator can be configured
for either crystal or external clock input. An internal
loop-back capability allows onboard diagnostics. The
2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to initialize both UARTs concurrently. The
2552 is available in the 44-PLCC package.
APPLICATIONS
FEATURES
Added feature in devices with top marking "A2
YYWW" and newer:
■
5 Volt Tolerant Inputs
•
Pin-to-pin and functionally compatible to National
PC16552 and Exar’s XR16L2752 and XR16C2852
•
4 Mbps transmit/receive operation (64 MHz
External Clock Frequency)
•
2 Independent UART Channels
■
■
Register Set Compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable RX FIFO Trigger Levels
Fixed Transmit FIFO interrupt trigger level
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
■
■
■
■
•
DMA operation and DMA monitoring via TXRDY#
and RXRDY# pins
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. ST16C2552 B
LOCK
D
IAGRAM
•
UART internal register sections A & B may be
written to concurrently
•
Multi-Function
output allows
functions with few I/O pins
even, odd, or no parity
more
package
•
Programmable character lengths (5, 6, 7, 8) with
•
Crystal oscillator or external clock input
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
3.3V or 5V VCC
GND
UART Channel A
UART
Regs
BRG
8-bit Data
Bus
Interface
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
Crystal Osc/Buffer
Modem Control Logic
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2552BLK
TXA (or TXIRA)
UART Channel B
(same as Channel A)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
REV. 4.2.1
TXRDYA#
DSRA#
41
44
43
42
40
6
5
4
3
2
1
CTSA#
CDA#
RIA#
VCC
D4
D3
D2
D1
D0
D5
D6
D7
A0
XTAL1
7
8
9
10
11
39
38
37
36
RXA
TXA
DTRA#
RTSA#
35 MFA#
GND 12
XTAL2
A1
13
14
ST16C2552
44-pin PLCC
34
33
32
31
INTA
VCC
TXRDYB#
RIB#
A2 15
CHSEL 16
INTB
17
18
MFB# 19
IOW# 20
RESET 21
GND 22
RTSB# 23
IOR# 24
RXB 25
TXB 26
DTRB# 27
CTSB# 28
30 CDB#
29
DSRB#
ORDERING INFORMATION
P
ART
N
UMBER
ST16C2552CJ44
ST16C2552IJ44
P
ACKAGE
44-Lead PLCC
44-Lead PLCC
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
CS#
2
ST16C2552
REV. 4.2.1
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
44-PLCC
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
15
14
10
9
8
7
6
5
4
3
2
24
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between
the user CPU and the 2552.
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A3. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see Figures
16
-
21
.
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see Figures
16
-
21
.
IOW#
20
I
CS#
18
I
CHSEL
16
I
INTA
34
O
INTB
17
O
TXRDYA#
1
O
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. If it is not used, leave it
unconnected.
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. If it is not used, leave it unconnected.
TXRDYB#
32
O
MODEM OR SERIAL I/O INTERFACE
3
ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Pin Description
N
AME
MFA#
44-PLCC
P
IN
#
35
T
YPE
O
D
ESCRIPTION
Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-
OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0 when MCR
bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after
a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.
See
Table 2
for more details.
If it is not used, leave it unconnected.
MFB#
19
O
Multi-Function Output ChannelB. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0 when MCR
bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after
a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See
Table 2
for more details.
If it is not used, leave it unconnected.
TXA
RXA
RTSA#
CTSA#
DTRA#
DSRA#
CDA#
38
39
36
40
37
41
42
O
I
O
I
O
I
I
UART channel A Transmit Data. If it is not used, leave it unconnected.
UART channel A Receive Data. Normal receive data input must idle at logic 1 condi-
tion. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose output. If it is not
used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel A Data-Terminal-Ready (active low) or general purpose output. If it is
not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
REV. 4.2.1
4
ST16C2552
REV. 4.2.1
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Pin Description
N
AME
RIA#
TXB
RXB
RTSB#
CTSB#
DTRB#
DSRB#
CDB#
RIB#
44-PLCC
P
IN
#
43
26
25
23
28
27
29
30
31
T
YPE
I
O
I
O
I
O
I
I
I
D
ESCRIPTION
UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel B Transmit Data. If it is not used, leave it unconnected.
UART channel B Receive Data. Normal receive data input must idle at logic 1 condi-
tion. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel B Request-to-Send (active low) or general purpose output. If it is not
used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel B Data-Terminal-Ready (active low) or general purpose output. If it is
not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
11
13
21
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during reset period (see External
Reset Conditions).
3.3V to 5V power supply. All inputs are 5V tolerant for devices with top marking of
"A2 YYWW" and newer.
Power supply common, ground.
VCC
GND
44, 33
22, 12
Pwr
Pwr
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
京公网安备 11010802033920号
EEWORLD
