ST16C454
QUAD UNIVERSAL ASYNCHRONOUS
RECEIVER/TRANSMITTER (UART)
DESCRIPTION
-CDA
GND
RXA
-RIA
PLCC Package
INTSEL
68
67
66
65
64
63
62
61
9
8
7
6
5
4
3
2
1
-CDD
VCC
RXD
-RID
D7
D6
D5
D4
D3
D2
D1
D0
The ST16C454 is a universal asynchronous receiver
and transmitter (UART) with a dual foot print interface.
The 454 is an enhanced UART with data rates up to
1.5Mbps and software compatible to ST16C450.
Onboard status registers provide the user with error
indications, operational status, and modem interface
control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows
onboard diagnostics. The ST16C454 offer an additional
68 mode which allows easy integration with Motorola,
and other popular microprocessors. The 454 combines
the package interface modes of the ST16C454 on a
single integrated chip with a selection pin.
-DSRA
-CTSA
-DTRA
VCC
-RTSA
INTA
-CSA
TXA
-IOW
TXB
-CSB
INTB
-RTSB
GND
-DTRB
-CTSB
-DSRB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
54
53
-DSRD
-CTSD
-DTRD
GND
-RTSD
INTD
-CSD
TXD
-IOR
TXC
-CSC
INTC
-RTSC
VCC
-DTRC
-CTSC
-DSRC
ST16C454CJ68
16 MODE
52
51
50
49
48
47
46
45
44
-CDB
RXB
RESET
GND
VCC
RXC
-RIC
62
-RID
XTAL1
XTAL2
16/-68
FEATURES
•
Software compatibility with the Industry Standard
16C450
•
2.97 to 5.5 volt operation
•
Intel or Motorola data bus interface select
•
1.5 Mbps transmit/receive operation (24MHz)
•
Independent transmit and receive control
•
Software selectable Baud Rate Generator
•
Modem control signals (-CTS, -RTS, -DSR, -DTR,
-RI, -CD)
•
Programmable character lengths (5, 6, 7, 8)
•
Even, odd, or no parity bit generation and detection
•
Internal loop-back diagnostics
•
TTL compatible inputs, outputs
•
Low power
-DSRA
-CTSA
-DTRA
VCC
-RTSA
-IRQ
-CS
TXA
R/-W
TXB
A3
N.C.
-RTSB
GND
-DTRB
-CTSB
-DSRB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
68
67
66
65
64
63
61
60
59
58
57
56
55
54
9
8
7
6
5
4
3
2
1
-CDD
-CDA
GND
VCC
RXD
RXA
-RIA
N.C.
D7
D6
D5
D4
D3
D2
D1
D0
-CDC
-RIB
A2
A1
A0
N.C.
N.C.
-DSRD
-CTSD
-DTRD
GND
-RTSD
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
-RTSC
VCC
-DTRC
-CTSC
-DSRC
ST16C454CJ68
68 MODE
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-RIC
-CDB
RXB
-RESET
A2
A1
16/-68
A0
XTAL1
XTAL2
GND
VCC
RXC
ORDERING INFORMATION
Part number
Package
Operating temperature
Device Status
ST16C454CJ68
ST16C454IJ68
68-Lead PLCC
68-Lead PLCC
0° C to + 70° C
-40° C to + 85° C
Active
Active
Rev. 3.31
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
-CDC
-RIB
N.C.
N.C.
43
ST16C454
Figure 2, Block Diagram in 16 Mode
D0-D7
-IOR
-IOW
RESET
Register
Select
Logic
Data bus
&
Control Logic
Transmit
Holding
Registers
Transmit
Shift
Register
TX A-D
A0-A2
-CS A-D
Inter Connect Bus Lines
&
Control signals
Receive
Holding
Registers
Receive
Shift
Register
RX A-D
INT A-D
INTSEL
Interrupt
Control
Logic
-DTR A-D
-RTS A-D
Clock
&
Baud Rate
Generator
XTAL1
Modem
Control
Logic
-CTS A-D
-RI A-D
-CD A-D
-DSR A-D
XTAL2
Rev. 3.31
2
ST16C454
Figure 3, Block Diagram in 68 Mode
D0-D7
R/-W
-RESET
Register
Select
Logic
Data bus
&
Control Logic
Transmit
Holding
Registers
Transmit
Shift
Register
TX A-D
A0-A4
-CS
Inter Connect Bus Lines
&
Control signals
Receive
Holding
Registers
Receive
Shift
Register
RX A-D
-IRQ
Interrupt
Control
Logic
-DTR A-D
-RTS A-D
Clock
&
Baud Rate
Generator
Modem
Control
Logic
-CTS A-D
-RI A-D
-CD A-D
-DSR A-D
XTAL1
XTAL2
Rev. 3.31
3
ST16C454
SYMBOL DESCRIPTION
Symbol
16/-68
Pin
31
Signal
type
I
Pin Description
16/68 Interface Type Select (input with internal pull-up). - This input
provides the 16 (Intel) or 68 (Motorola) bus interface type select. The
functions of -IOR, -IOW, INT A-D, and -CS A-D are re-assigned with
the logical state of this pin. When this pin is a logic 1, the 16 mode
interface ST16C454 is selected. When this pin is a logic 0, the 68
mode interface (ST68C454) is selected. When this pin is a logic 0,
-IOW is re-assigned to R/-W, RESET is re-assigned to -RESET, -
IOR is not used, and INT A-D(s) are connected in a WIRE-OR”
configuration. The WIRE-OR outputs are connected internally to the
open source IRQ signal output.
Address-0 Select Bit. Internal registers address selection in 16 and
68 modes.
Address-1 Select Bit. Internal registers address selection in 16 and
68 modes.
Address-2 Select Bit. - Internal registers address selection in 16
and 68 modes.
Address 3-4 Select Bits. - When the 68 mode is selected, these
pins are used to address or select individual UART’s (providing -
CS is a logic 0). In the 16 mode, these pins are reassigned as chip
selects, see -CSB and -CSC.
Chip Select. (active low) - In the 68 mode, this pin functions as a
multiple channel chip enable. In this case, all four UART’s (A-D)
are enabled when the -CS pin is a logic 0. An individual UART
channel is selected by the data contents of address bits A3-A4.
When the 16 mode is selected, this pin functions as -CSA, see
definition under -CS A-B.
A0
34
I
A1
33
I
A2
32
I
A3-A4
20,50
I
-CS
16
I
-CS A-B
-CS C-D
16,20
50,54
I
Chip Select A, B, C, D (active low) - This function is associated with
the 16 mode only, and for individual channels, “A” through “D.”
When in 16 Mode, these pins enable data transfers between the
user CPU and the ST16C454 for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing
a logic 0 on the respective -CS A-D pin. When the 68 mode is
selected, the functions of these pins are reassigned. 68 mode
functions are described under the their respective name/pin
headings.
Rev. 3.31
4
ST16C454
SYMBOL DESCRIPTION
Symbol
D0-D2
D3-D7
Pin
66-68
1-5
Signal
type
I/O
Pin Description
Data Bus (Bi-directional) - These pins are the eight bit, three state
data bus for transferring information to or from the controlling CPU.
D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.
GND
GND
INT A-B
INT C-D
6,23
40,57
15,21
49,55
Pwr
Signal and power ground.
O
Interrupt A, B, C, D (active high) - This function is associated with
the 16 mode only. These pins provide individual channel inter-
rupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a
logic 1, interrupts are enabled in the interrupt enable register (IER),
and when an interrupt condition exists. Interrupt conditions in-
clude: receiver errors, available receiver buffer data, transmit
buffer empty, or when a modem status flag is detected. When the
68 mode is selected, the functions of these pins are reassigned. 68
mode functions are described under the their respective name/pin
headings.
Interrupt Select. (active high, with internal pull-down) - This
function is associated with the 16 mode only. When the 16 mode
is selected, this pin can be used in conjunction with MCR bit-3 to
enable or disable the three state interrupts, INT A-D or override
MCR bit-3 and force continuous interrupts. Interrupt outputs are
enabled continuously by making this pin a logic 1. Making this pin
a logic 0 allows MCR bit-3 to control the three state interrupt output.
In this mode, MCR bit-3 is set to a logic “1” to enable the three state
outputs. This pin is disabled in the 68 mode.
Read strobe. (active low Strobe) - This function is associated with
the 16 mode only. A logic 0 transition on this pin will load the
contents of an Internal register defined by address bits A0-A2 onto
the ST16C454 data bus (D0-D7) for access by an external CPU.
This pin is disabled in the 68 mode.
Write strobe. (active low strobe) - This function is associated with
the 16 mode only. A logic 0 transition on this pin will transfer the
contents of the data bus (D0-D7) from the external CPU to an
internal register that is defined by address bits A0-A2. When the
16 mode is selected, this pin functions as R/-W, see definition under
INTSEL
65
I
-IOR
52
I
-IOW
18
I
Rev. 3.31
5
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