xr
FEBRUARY 2005
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.1
GENERAL DESCRIPTION
The XR16C2852
1
(2852) is a dual universal
asynchronous receiver and transmitter (UART). The
device operates at 2.97V to 5.5V and is pin-to-pin
compatible to Exar’s ST16C2552 and XR16L2752.
The 2852 register set is compatible to the
ST16C2552 and the XR16L2752 enhanced features.
It supports the Exar’s enhanced features of 128 bytes
of TX and RX FIFOs, programmable FIFO trigger
level and FIFO level counters, automatic hardware
(RTS/CTS) and software flow control, automatic RS-
485 half duplex direction control output and a
complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnotics. Independent programmable baud
rate generators are provided in each channel to
select data rates up to 3.125 Mbps at 5V. The 2852 is
available in the 44-pin PLCC package.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,949,787
FEATURES
Added feature in devices with a top mark date code of
"F2 YYWW" and newer:
■
■
5V tolerant inputs
0 ns address hold time (T
AH
)
•
Pin-to-pin compatible to Exar’s ST16C2552 and
XR16L2752
•
Improved version of PC16C552
•
Two independent UART channels
■
■
■
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
Register set compatible to 16C550
Up to 3 Mbps at 5V, and 2 Mbps at 3.3V
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Automatic RS-485 Half-duplex Direction
Control Output
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
•
Alternate Function Register
•
Device Identification and Revision
•
Crystal oscillator or external clock input
•
2.97 to 5.5 volt operation
•
Industrial and commercial temperature ranges
F
IGURE
1. XR16C2852 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
2.97V to 5.5V VCC
GND
UART Channel A
UART
Regs
BRG
8-bit Data
Bus
Interface
128 Byte TX FIFO
TX & RX
IR
ENDEC
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
TXA (or TXIRA)
128 Byte RX FIFO
UART Channel B
(same as Channel A)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Crystal Osc/Buffer
Modem Control Logic
Reset
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
xr
REV. 2.1.1
TXRDYA#
DSRA#
41
44
43
42
40
6
5
4
3
2
1
CTSA#
CDA#
RIA#
VCC
D4
D3
D2
D1
D0
D5
D6
D7
A0
XTAL1
7
8
9
10
11
39
38
37
36
RXA
TXA
DTRA#
RTSA#
GND 12
XTAL2
A1
13
14
XR16C2852
44-pin PLCC
35 MFA#
34
33
32
31
INTA
VCC
TXRDYB#
RIB#
A2 15
CHSEL 16
INTB 17
CS# 18
MFB# 19
IOW# 20
RESET 21
GND 22
RTSB# 23
IOR# 24
RXB 25
TXB 26
DTRB# 27
CTSB# 28
30 CDB#
29
DSRB#
ORDERING INFORMATION
P
ART
N
UMBER
XR16C2852CJ
XR16C2852IJ
P
ACKAGE
44-PLCC
44-PLCC
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
2
xr
REV. 2.1.1
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
PIN DESCRIPTIONS
Pin Description
N
AME
44-PLCC
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
15
14
10
9
8
7
6
5
4
3
2
24
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between the
user CPU and the 2852.
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is LOW. A LOW on the CHSEL selects the UART channel B while a HIGH
selects UART channel A. Normally, CHSEL could just be an address line from the
user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily
override CHSEL function, allowing the user to write to both channel register simulta-
neously with one write cycle when CS# is LOW. It is especially useful during the ini-
tialization routine.
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see
Figures 20
-
25
.
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see
Figures 20
-
25
.
IOW#
20
I
CS#
18
I
CHSEL
16
I
INTA
INTB
TXRDYA#
34
17
1
O
O
O
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. See
Table 2 on page 9.
If this output is
not used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B.
See
Table 2 on page 9.
If this output is not
used, leave it unconnected.
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is a logic 0. If this output is not used, leave it
unconnected.
TXRDYB#
32
O
MODEM OR SERIAL I/O INTERFACE
TXA
38
O
3
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
Pin Description
N
AME
RXA
44-PLCC
P
IN
#
39
T
YPE
I
D
ESCRIPTION
xr
REV. 2.1.1
UART channel A Receive Data or infrared receive data. Normal receive data input
must idleHIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin
is not used, tie it to VCC or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose output. This output
must be asserted (LOW) prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3]. If this output is not used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose output. If this
output is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used.
UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used.
UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used.
Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUD-
OUTA#, or RXRDYA# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a
reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers.
See
Table 2 on page 9
for more details.
If this output is not used, leave it unconnected.
RTSA#
36
O
CTSA#
40
I
DTRA#
DSRA#
CDA#
RIA#
MFA#
37
41
42
43
35
O
I
I
I
O
TXB
26
O
UART channel B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If this output is not used, leave it uncon-
nected.
UART channel B Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin
is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RXB
25
I
4
xr
REV. 2.1.1
XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
Pin Description
N
AME
RTSB#
44-PLCC
P
IN
#
23
T
YPE
O
D
ESCRIPTION
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3]. If this output is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose output. If this
output is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used.
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used.
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used.
Multi-Function Output Channel B. This output pin can function as the OP2B#, BAUD-
OUTB#, or RXRDYB# pin. One of these output signal functions can be selected by
the user programmable bits 1-2 of the Alternate Function Register (AFR). These sig-
nal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW when MCR bit-
3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 0 condition after a
reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate clock
output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data transfers.
See
Table 2 on page 9
for more details.
If this output is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
11
13
21
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset the internal
registers and all outputs. The UART transmitter output will be held HIGH, the receiver
input will be ignored and outputs are reset during reset period (see
Table 16 on
page 38).
2.97V to 5.5V power supply. All inputs are 5V tolerant for devices with top mark date
code of "F2 YYWW" and newer.
Power supply common, ground.
CTSB#
28
I
DTRB#
DSRB#
CDB#
RIB#
MFB#
27
29
30
31
19
O
I
I
I
O
VCC
GND
44, 33
22, 12
Pwr
Pwr
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
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