xr
APRIL 2005
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
GENERAL DESCRIPTION
The XR16L2750
1
(2750) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
operates from 2.25 to 5.5 Volt supply range and is
pin-to-pin compatible to Exar’s ST16C2550 and
XR16C2850 except the 48-TQFP package. The 2750
register set is compatible to the ST16C2550 and the
XR16C2850 enhanced features. It supports the
Exar’s enhanced features of 64 bytes of TX and RX
FIFOs, programmable FIFO trigger level and FIFO
level counters, automatic hardware (RTS/CTS) and
software flow control, automatic RS-485 half duplex
direction control output and a complete modem
interface. Onboard registers provide the user with
operational status and data error flags. An internal
loopback capability allows system diagnostics.
Independent programmable baud rate generators are
provided in each channel to select data rates up to
6.25 Mbps at 5 Volt and 8X sampling clock. The 2750
is available in 48-pin TQFP and 44-pin PLCC
packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,949,787
FEATURES
•
2.25 to 5.5 Volt Operation
•
5 Volt Tolerant Inputs
•
Pin-to-pin compatible to Exar’s ST16C2550 and
TI’s TL16C752B on the 48-TQFP package
•
Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
•
Two independent UART channels
■
■
■
■
■
■
■
■
■
■
■
■
APPLICATIONS
Reg set compatible to 16C2550 and 16C2850
Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt,
and 3 Mbps at 2.5 Volt with 8X sampling rate
Transmit and Receive FIFOs of 64 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Automatic RS-485 Half-duplex Direction
Control Output via RTS#
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16L2750 B
LOCK
D
IAGRAM
•
Device Identification and Revision
•
Crystal oscillator or external clock input
•
Industrial and commercial temperature ranges
•
48-TQFP and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset
8-bit Data
Bus
Interface
* 5 Volt Tolerant Inputs
(Except XTAL1)
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
2.25 to 5.5 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
64 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
2750BLK
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
xr
REV. 1.2.1
TXRDYA#
DSRA#
VCC
RIA#
CTSA#
38
CDA#
48
45
43
42
41
40
47
46
44
39
37
NC
D4
D3
D2
D1
D0
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
1
2
3
4
5
6
7
8
9
36
35
34
33
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
XR16L2750
48-pin TQFP
32
31
30
29
28
27
26
25
CSA# 10
CSB# 11
NC 12
15
13
18
19
20
22
16
14
17
21
23
24
GND
DSRB#
RTSB#
RXRDYB#
TXRDYA#
DSRA#
41
CTSB#
CDB#
XTAL2
IOW#
XTAL1
IOR#
RIB#
44
43
42
40
6
5
4
3
2
1
CTSA#
CDA#
RIA#
VCC
D4
D3
D2
D1
D0
NC
D5
D6
D7
RXB
RXA
7
8
9
10
11
39
38
37
36
RESET
DTRB#
DTRA#
RTSA#
TXRDYB# 12
TXA
TXB
13
14
XR16L2750
44-pin PLCC
35 OP2A#
34
33
32
31
RXRDYA#
INTA
INTB
A0
OP2B# 15
CSA# 16
CSB# 17
XTAL1 18
XTAL2 19
IOW# 20
CDB# 21
GND 22
RXRDYB# 23
IOR# 24
DSRB# 25
RIB# 26
RTSB# 27
CTSB# 28
30 A1
29
A2
ORDERING INFORMATION
P
ART
N
UMBER
XR16L2750CJ
XR16L2750IJ
XR16L2750CM
XR16L2750IM
P
ACKAGE
44-Lead PLCC
44-Lead PLCC
48-Lead TQFP
48-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
2
xr
REV. 1.2.1
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
29
30
31
9
8
7
6
5
4
3
2
24
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
Table 2
. If it is not
used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2
. If it is not
used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 3
. If it is not
used, leave it unconnected.
IOW#
20
15
I
CSA#
CSB#
INTA
16
17
33
10
11
30
I
I
O
INTB
32
29
O
TXRDYA#
1
43
O
RXRDYA#
34
31
O
TXRDYB#
12
6
O
3
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
Pin Description
N
AME
RXRDYB#
44-PLCC
P
IN
#
23
48-TQFP
P
IN
#
18
T
YPE
O
D
ESCRIPTION
xr
REV. 1.2.1
UART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. See
Table 2
. If it is not
used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
13
7
O
UART channel A Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
UART channel A Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles at
LOW but can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose out-
put. This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto
RS485 half-duplex direction control, see FCTR[3] and EMSR[3].
UART channel A Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. This output should not be used as a general out-
put else it will disturb the INTA output functionality.
UART channel B Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
RXA
11
5
I
RTSA#
36
33
O
CTSA#
40
38
I
DTRA#
DSRA#
37
41
34
39
O
I
CDA#
42
40
I
RIA#
43
41
I
OP2A#
35
32
O
TXB
14
8
O
4
xr
REV. 1.2.1
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
Pin Description
N
AME
RXB
44-PLCC
P
IN
#
10
48-TQFP
P
IN
#
4
T
YPE
I
D
ESCRIPTION
UART channel B Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles at
logic 0 but can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto
RS485 half-duplex direction control, see FCTR[3] and EMSR[3].
UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to
the three state mode and OP2B# output HIGH when MCR[3] is set to a
logic 0. See MCR[3]. This output should not be used as a general out-
put else it will disturb the INTB output functionality.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
18
19
39
13
14
36
I
O
I
Crystal or external clock input. Caution: this input is not 5V tolerant.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held HIGH, the receiver input will be ignored and outputs are
reset during reset period (see External Reset Conditions).
2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V toler-
ant.
Power supply common, ground.
No Connection.
RTSB#
27
22
O
CTSB#
28
23
I
DTRB#
DSRB#
38
25
35
20
O
I
CDB#
21
16
I
RIB#
26
21
I
OP2B#
15
9
O
VCC
GND
N.C.
44
22
none
42
17
12, 24, 25,
37
Pwr
Pwr
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
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