EH3525ETTTS-4.096M TR
Series
RoHS Compliant (Pb-free) 5.0V 4 Pad 3.2mm x 5mm
Ceramic SMD HCMOS/TTL High Frequency Oscillator
Frequency Tolerance/Stability
±25ppm Maximum
Operating Temperature Range
-40°C to +85°C
Duty Cycle
50 ±5(%)
RoHS
Pb
Packaging Options
Tape & Reel
EH35 25 ET T TS -4.096M TR
Nominal Frequency
4.096MHz
Pin 1 Connection
Tri-State (Disabled Output: High Impedance)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
4.096MHz
±25ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year Aging at 25°C,
Shock, and Vibration)
±5ppm/year Maximum
-40°C to +85°C
5.0Vdc ±10%
50mA Maximum (No Load)
2.4Vdc Minimum with TTL Load, Vdd-0.4Vdc Minimum with HCMOS Load (IOH = -16mA)
0.4Vdc Maximum with TTL Load, 0.5Vdc Maximum with HCMOS Load (IOL = +16mA)
6nSec Maximum (Measured at 0.8Vdc to 2.0Vdc with TTL Load or at 20% to 80% of waveform with
HCMOS Load)
50 ±5(%) (Measured at 50% of waveform with TTL Load or with HCMOS Load)
10TTL Load or 50pF HCMOS Load Maximum
CMOS
Tri-State (Disabled Output: High Impedance)
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to
enable output.
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±30pSec Typical
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, MEthod 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 3/12/2011 | Page 1 of 7
EH3525ETTTS-4.096M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% or 2.0V
DC
50% or 1.4V
DC
20% or 0.8V
DC
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
2TTL
10LSTTL
1TTL
R
L
Value
(Ohms)
390
780
1100
2000
2200
C
L
Value
(pF)
15
15
6
15
3
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 3/12/2011 | Page 3 of 7
EH3525ETTTS-4.096M TR
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 3/12/2011 | Page 4 of 7
PCB Design
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