HCS74T
Data Sheet
July 1999
File Number
4615.1
Radiation Hardened Dual-D Flip-Flop with
Set and Reset
Intersil’s Satellite Applications
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil HCS74T is a Radiation Hardened Positive Edge
Triggered Flip-Flop with set and reset.
The HCS74T utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Flow
TM
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions, SOS Process
- SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
- Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
• 3 Micron Radiation Hardened SOS CMOS
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- V
IL
= 30% of V
CC
Max
- V
IH
= 70% of V
CC
Min
• Input Current Levels Ii
≤
5µA at V
OL
, V
OH
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCS74T are
contained in SMD 5962-95782.
A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Pinouts
HCS74T (SBDIP), CDIP2-T14
TOP VIEW
R1 1
D1 2
CP1 3
S1N 4
Q1 5
14 V
CC
13 R2N
12 D2
11 CP2
10 S2N
9 Q2
8 Q2N
Ordering Information
ORDERING
INFORMATION
5962R9578201TCC
5962R9578201TXC
PART
NUMBER
HCS74DTR
HCS74KTR
TEMP.
RANGE
(
o
C)
-55 to 125
-55 to 125
R1
D1
CP1
S1
Q1
Q1
GND
Q1N 6
GND 7
HCS74T (FLATPACK), CDFP3-F14
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R2
D2
CP2
S2
Q2
Q2
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
HCS74T
Die Characteristics
DIE DIMENSIONS:
(2261µm x 2235µm x 533µm
±51µm)
89 x 88 x 21mils
±2mil
METALLIZATION:
Type: Al Si
Thickness: 11k
Å
±1k
Å
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13k
Å
±2.6k
Å
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
192
PROCESS:
CMOS SOS
Metallization Mask Layout
HCS74T
D1
(2)
R1
(1)
V
CC
(14)
CP1 (3)
(13) R2
NC
(12) D2
S1 (4)
NC
Q1 (5)
(11) CP2
(10) S2
Q1 (6)
(7)
GND
(8)
Q2
(9)
Q2
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
3
京公网安备 11010802033920号
EEWORLD
