xr
JULY 2005
PRELIMINARY
XRT91L80
REV. P1.1.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION
The XRT91L80 is a fully integrated SONET/SDH
transceiver for SONET OC-48/STM-16 applications
supporting the use of Forward Error Correction (FEC)
capability. The transceiver includes an on-chip Clock
Multiplier Unit (CMU), which uses a high frequency
Phase-Locked Loop (PLL) to generate the high-
speed transmit serial clock from a slower external
clock reference. It also provides Clock and Data
Recovery (CDR) functions by synchronizing its on-
chip Voltage Controlled Oscillator (VCO) to the
incoming serial data stream. The chip provides serial-
to-parallel and parallel-to-serial converters and 4-bit
LVDS system interfaces in both receive and transmit
directions. The transmit section includes a 4x9 Elastic
Buffer (FIFO) to absorb any phase differences
between the transmitter clock input and the internally
generated transmitter reference clock. In the event of
an overflow, an internal FIFO control circuit outputs
an OVERFLOW indication. The FIFO under the
F
IGURE
1. B
LOCK
D
IAGRAM OF
XRT91L80
control of the FIFO_AUTORST pin can automatically
recover from an overflow condition. The operation of
the device can be monitored by checking the status
of the LOCKDET_CMU, LOCKDET_CDR, and
LOSDET output signals. An on-chip phase/frequency
detector and charge-pump offers the ability to form a
de-jittering PLL with an external VCXO that can be
used in loop timing mode to clean up the recovered
clock in the receive section.
APPLICATIONS
•
SONET/SDH-based Transmission Systems
•
Add/Drop Multiplexers
•
Cross Connect Equipment
•
ATM and Multi-Service Switches and Routers
•
DSLAMS
•
SONET/SDH Test Equipment
•
DWDM Termination Equipment
STS-48 TRANSCEIVER
FIFO_RST
FIFO_AUTORST
TXDI0P/N
TXDI1P/N
TXDI2P/N
TXDI3P/N
TXPCLKIP/N
TXPCLKOP/N
TXCLKO16P/N
TXCLKO16DIS
Div by 4
Div by 16
WP
4x9 FIFO
PISO
(Parallel Input
Serial Output)
TXOP/N
Re-Timer
RP
CMU
DLOOP
RLOOPS
RLOOPP
RXDO0P/N
RXDO1P/N
RXDO2P/N
RXDO3P/N
RXPCLKOP/N
RXCLKO16P/N
Div by 4
Div by 16
SIPO
(Serial Input
Parallel Output)
CDR
RXIP/N
DISRD
LOSDMUTE
TDO
TDI
TCK
TMS
TRST
JTAG
Serial
Microprocessor
Hardware
Control
PFD
& Charge Pump
RLOOPS
RLOOPP
DLOOP
LOOPTM_JA
LOOPTM_NOJA
LOOPBW
LOCKDET_CMU
LOCKDET_CDR
LOSDET
SDEXT
POLARITY
TEST
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
REFCLKP/N
VCXO_INP/N
ALTFREQSEL
VCXO_SEL
VCXO_LOCKEN
VCXO_LOCK
CPOUT
OVERFLOW
CS
SCLK
SDI
SDO
HOST/HW
INT
RESET
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
FEATURES
xr
REV. P1.1.0
•
2.488 / 2.666 Gbps Transceiver
•
Targeted for SONET OC-48/SDH STM-16 Applications
•
Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of
2.666 Gbps
•
Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-
to-parallel converter, and clock data recovery (CDR) functions
•
4-bit LVDS signaling data paths running at 622.08/666.51 Mbps compliant with OIF SFI-4 Implimentation
Agreement
•
Non-FEC and FEC rate REFCLKP/N single reference input port
•
Supports 77.76/83.31 MHz or 155.52/166.63 MHz transmit and receive external reference input port
•
Optional VCXO input port support multiple de-jittering modes
•
On-chip phase detector and charge pump for external VCXO based de-jittering PLL
•
Internal FIFO decouples transmit parallel clock input and transmit parallel clock output
•
Provides Local, Remote Serial, Remote Parallel and Split Loopback modes as well as Loop Timing mode
•
Diagnostics features include various lock detect functions and transmit CMU and receive CDR Lock Detect
•
Host mode serial microprocessor interface simplifies monitor and control
•
Meets Telcordia, ANSI and ITU-T jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance
specification, GR-253 CORE, GR-253 ILR SONET Jitter specifications.
•
Operates at 1.8V CMOS and CML with 3.3V I/O
•
490mW Typical Power Dissipation
•
Package: 12 x 12 mm 196-pin STBGA
•
IEEE 1149.1 Compatable JTAG port
PRODUCT ORDERING INFORMATION
P
RODUCT
N
UMBER
XRT91L80IB
P
ACKAGE
T
YPE
196 STBGA
O
PERATING
T
EMPERATURE
R
ANGE
-40° to +85°
C
C
2
REV. P1.1.0
xr
A AGND_RX
NC
DGND
RXCLKO16P RXCLKO16N
VDD3.3
SDI
VDD1.8
RXDO3P
CS
RLOOPP
DGND
TRST
LOSDMUTE
B AGND_RX
DGND
NC
SDEXT
DLOOP
VDD1.8
DGND
SCLK
RESET
VDD1.8
TDO
DGND
AGND_RX
RXDO3N
C
POLARITY
LOSDET
LOOPTM_JA LOCKDET_CDR
SDO
HOST/HW
RLOOPS
RXDO2P
INT
DISRD
RXIP
AGND_RX
AGND_RX
RXDO1P
D
AGND_RX
AVDD1.8_RX
VDD3.3
VDD3.3
VDD3.3
VDD1.8
RXIN
AGND_RX
AVDD3.3_RX AVDD1.8_RX AVDD1.8_RX AVDD1.8_RX
RXDO2N
RXDO1N
E AGND_RX
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
VDD3.3
AGND_RX
AVDD3.3_RX
VDD1.8
RXDO0P RXPCLKOP
F
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
DGND
XRES1N
AGND_RX
AVDD1.8_RX
DGND
RXDO0N RXPCLKON
G
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
XRES1P
AGND_RX
AVDD1.8_RX
DGND
DGND
DGND
DGND
H AGND_RX
AGND_RX
TGND
TGND
TGND
TGND
TGND
AGND_RX
AGND_RX
TGND
DGND
DGND
TXDI0P
TXPCLKIP
PRELIMINARY
F
IGURE
2. 196 BGA P
INOUT OF
THE XRT91L80 (T
OP
V
IEW
)
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
3
AVDD1.8_TX
TGND
TGND
TGND
TGND
TGND
AGND_TX
TGND
TGND
TGND
TGND
TGND
DGND
AGND_TX
AGND_TX AVDD1.8_TX AVDD1.8_TX AVDD1.8_TX
VDD1.8
AGND_TX
AGND_TX
VCXO_SEL
LOOPBW
TDI
VDD1.8
TCK
VCXO_INN
AGND_TX
REFCLKN
AGND_TX
AGND_TX
CPOUT
3
4
5
6
7
8
9
10
J AVDD1.8_TX
AGND_TX
AGND_TX
TGND
DGND
DGND
TXDI0N
TXPCLKIN
K
TXOP
AGND_TX
AGND_TX
TGND
VDD1.8
DGND
TXDI2P
TXDI1P
L
TXON
AGND_TX
VDD1.8
DGND
DGND
TXDI2N
TXDI1N
M AGND_TX
AVDD1.8_TX
AVDD1.8_TX
VDD1.8
VDD1.8
TXCLKO16DIS OVERFLOW
TXDI3P
N
TMS
LOCKDET_CMU
VCXO_LOCK AVDD1.8_TX TXCLKO16PTXCLKO16N FIFO_AUTORST FIFO_RST
TXDI3N
P ALTFREQSEL LOOPTM_NOJA VCXO_LOCKEN VCXO_INP AVDD3.3_TX REFCLKP
AVDD3.3_TX TXPCLKOP TXPCLKON
DGND
VDD3.3
VDD3.3
1
2
11
12
13
14
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM OF
XRT91L80 ...................................................................................................................................... 1
FEATURES
......................................................................................................................................................2
PRODUCT ORDERING INFORMATION ..................................................................................................2
F
IGURE
2. 196 BGA P
INOUT OF
THE XRT91L80 (T
OP
V
IEW
).......................................................................................................... 3
T
ABLE OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS ..........................................................................................................4
S
ERIAL
M
ICROPROCESSOR INTERFACE
............................................................................................................4
H
ARDWARE COMMON CONTROL
......................................................................................................................5
T
RANSMITTER
S
ECTION
..................................................................................................................................6
RECEIVER SECTION
.........................................................................................................................................9
P
OWER AND
G
ROUND
..................................................................................................................................10
N
O
C
ONNECTS
.............................................................................................................................................11
JTAG ..........................................................................................................................................................12
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................13
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 13
1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 13
T
ABLE
1: R
EFERENCE
F
REQUENCY
O
PTIONS
(N
ON
-FEC
AND
FEC M
ODE
)...................................................................................... 13
1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 13
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
F
ORWARD
E
RROR
C
ORRECTION
.................................................................................... 13
2.0 RECEIVE SECTION .............................................................................................................................14
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
F
IGURE
4. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 14
T
ABLE
2: D
IFFERENTIAL
CML I
NPUT
S
WING
P
ARAMETERS
.............................................................................................................. 14
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
3: C
LOCK AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 15
2.3 EXTERNAL SIGNAL DETECTION ................................................................................................................. 15
T
ABLE
4: LOSD D
ECLARATION
P
OLARITY
S
ETTING
......................................................................................................................... 16
2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 16
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
SIPO ........................................................................................................................... 16
2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 16
F
IGURE
6. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 16
2.6 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 17
F
IGURE
7. LVDS
EXTERNAL BIASING RESISTORS
............................................................................................................................. 17
2.7 PARALLEL RECEIVE DATA OUTPUT MUTE UPON LOSD ........................................................................ 17
2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE ......................................................................................... 17
2.9 RECEIVE PARALLEL DATA OUTPUT TIMING ............................................................................................ 17
F
IGURE
8. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
.............................................................................................................................. 17
T
ABLE
5: R
ECEIVE
P
ARALLEL
D
ATA AND
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATIONS
........................................................................... 17
3.0 TRANSMIT SECTION ..........................................................................................................................18
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 18
F
IGURE
9. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................... 18
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 19
F
IGURE
10. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 19
T
ABLE
6: T
RANSMIT
P
ARALLEL
D
ATA AND
C
LOCK
I
NPUT
T
IMING
S
PECIFICATION
............................................................................... 19
T
ABLE
7: T
RANSMIT
P
ARALLEL
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATION
........................................................................................... 19
3.3 TRANSMIT FIFO ............................................................................................................................................. 19
F
IGURE
11. T
RANSMIT
FIFO
AND
S
YSTEM
I
NTERFACE
.................................................................................................................... 20
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 20
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 20
F
IGURE
12. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
PISO ......................................................................................................................... 20
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 21
T
ABLE
8: C
LOCK
M
ULTIPLIER
U
NIT
P
ERFORMANCE
......................................................................................................................... 21
3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 21
T
ABLE
9: L
OOP TIMING AND REFERENCE DE
-
JITTER CONFIGURATIONS
.............................................................................................. 22
F
IGURE
13. L
OOP
T
IMING
M
ODE
U
SING AN
E
XTERNAL
C
LEANUP
VCXO.......................................................................................... 22
3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 23
I
xr
REV. P1.1.0
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
F
IGURE
14. S
IMPLIFIED
D
IAGRAM OF THE
E
XTERNAL
L
OOP
F
ILTER
.................................................................................................. 23
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 23
F
IGURE
15. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE BLOCK
.............................................................................................................. 23
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 24
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 24
F
IGURE
16. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 24
4.2 PARALLEL REMOTE LOOPBACK ............................................................................................................... 24
F
IGURE
17. P
ARALLEL
R
EMOTE
L
OOPBACK
.................................................................................................................................... 24
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 25
F
IGURE
18. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 25
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 26
4.4.1 JITTER TOLERANCE: ................................................................................................................................................ 26
F
IGURE
19. J
ITTER
T
OLERANCE
M
ASK
............................................................................................................................................ 26
F
IGURE
20. 91L80 M
EASURED JITTER TOLERANCE WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT
2.488 G
BPS IN
STS-
48.................................................................................................................................................................................. 27
4.4.2 JITTER TRANSFER .................................................................................................................................................... 27
F
IGURE
21. 91L80 M
EASURED JITTER TRANSFER WITH EXTERNAL JITTER ATTENUATION ENABLED IN LOOPTIMING AT
2.488 G
BPS IN
STS-
48.................................................................................................................................................................................. 27
4.4.3 JITTER GENERATION................................................................................................................................................ 28
F
IGURE
22. 91L80 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
T
RANSMIT
J
ITTER
G
ENERATION AT
2.488 G
BPS
...................................... 28
F
IGURE
23. 91L80 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
R
ECEIVE
J
ITTER
G
ENERATION AT
2.488 G
BPS
........................................ 28
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ......................................................................... 29
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 29
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 29
F
IGURE
25. T
IMING
D
IAGRAM FOR THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 29
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 30
5.2.1
5.2.2
5.2.3
5.2.4
R/W (SCLK1)...............................................................................................................................................................
A[5:0] (SCLK2 - SCLK7).............................................................................................................................................
X (DUMMY BIT SCLK8) ..............................................................................................................................................
D[7:0] (SCLK9 - SCLK16)...........................................................................................................................................
30
30
30
30
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 30
6.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 31
T
ABLE
10:
T
ABLE
11:
T
ABLE
12:
T
ABLE
13:
T
ABLE
14:
T
ABLE
15:
T
ABLE
16:
T
ABLE
17:
T
ABLE
18:
M
ICROPROCESSOR
R
EGISTER
M
AP
................................................................................................................................ 31
M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
................................................................................................. 31
M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
................................................................................................. 32
M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
................................................................................................. 32
M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
................................................................................................. 33
M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
................................................................................................. 35
M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
................................................................................................. 35
M
ICROPROCESSOR
R
EGISTER
0
X
3E
H
B
IT
D
ESCRIPTION
................................................................................................. 37
M
ICROPROCESSOR
R
EGISTER
0
X
3F
H
B
IT
D
ESCRIPTION
................................................................................................. 37
7.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 38
A
BSOLUTE
M
AXIMUM
RATINGS .................................................................................................................. 38
POWER AND CURRENT DC E
LECTRICAL
C
HARACTERISTICS
.................................................................... 38
................................................................................................................................................................... 39
C
OMMON MODE
LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................ 39
................................................................................................................................................................... 39
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS .......................................................... 39
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS............................................................... 40
LVTTL/LVCMOS S
IGNAL
DC ELECTRICAL CHARACTERISTICS ........................................................... 40
ORDERING INFORMATION .................................................................................................................. 41
R
EVISION
H
ISTORY
...................................................................................................................................... 42
II
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