530UB844M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530UB844M000DGR

530UB844M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 844MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530UB844M000DGR Overview

CMOS/TTL Output Clock Oscillator, 844MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530UB844M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	844 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Display drive circuit for digital voltmeter

STK4301 power amplifier circuit diagram

AE sensor practical circuit diagram

Low power consumption, 5V drive, temperature compensated crystal oscillator circuit

Rotary switch made of shift register

Constant voltage drive circuit using op amp

cc2640 to cc2640R2F: After the release of Bluetooth 5 protocol, Nordic took the lead in launching the chip nrf52840 that supports ble5.0 protocol. The powerful configuration is simply outrageous for me who has used ti Blu...; fish001 Wireless Connectivity

What are OTP sheets and mask sheets? What is the difference between them?: OTP means one time program, one-time programming[/backcolor][/color][/size] [size=4][color=#000000][backcolor=white] [/backcolor][/color][/size] [size=4][color=#000000][backcolor=white]MTP means multi...; fish001 Analogue and Mixed Signal

A joke: [color=#333333][font=Arial,]Lao Zhou's daughter was born, and the doctor who delivered her was an acquaintance, Lao Liu. Lao Liu said, "There is good news and bad news. Which one do you want to hear f...; mmmllb Talking

[TI's first low-power design competition] MSP430FR5969 assigns variables to any FRAM address: [align=left][font=宋体]Just now a classmate in the group asked how to assign variables to [/font]FRAM[font=宋体] addresses. I guess there will be many experts who will tell you how to personalize [/font]....; littleshrimp Microcontroller MCU

Hello: [i=s]This post was last edited by qwqwer on 2017-5-16 11:46[/i] There are many categories of the electronics industry, such as computers (computers are divided into many parts, so I won’t go into deta...; qwqwer FPGA/CPLD

When programming the microcontroller in C, each file is compiled correctly, but an error occurs during Build: Hello everyone, When programming the microcontroller in C, all files are compiled correctly, but an error occurs during build: FATAL ERROR L250: CODE SIZE LIMIT IN RESTRICTED VERSION EXCEEDED MODULE: ...; nfwo Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components