4, 8, 16 MEG x 64
SDRAM DIMMs
SYNCHRONOUS
DRAM MODULE
FEATURES
• PC66-*, PC100- and PC133-compliant
• JEDEC-standard, 168-pin, dual in-line memory
module (DIMM)
• Utilizes 100 MHz*, 125 MHz and 133 MHz
SDRAM components
• Unbuffered
• 32MB (4 Meg x 64), 64MB (8 Meg x 64), 128MB
(16 Meg x 64)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
MT4LSDT464A, MT4LSDT864A
MT4LSDT1664A
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/datasheets/datasheet.html
PIN ASSIGNMENT (Front View)
168-Pin DIMM
OPTIONS
• Package
168-pin DIMM (gold)
MARKING
G
• Frequency/CAS Latency
133 MHz/CL = 2 (7.5ns, 133 MHz SDRAM)
133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs)
100 MHz/CL = 2 (8ns, 125 MHz SDRAMs)
66 MHz/CL = 2 (10ns, 100 MHz SDRAMs)
*32MB only
-13E
-133
-10E
-662*
KEY SDRAM COMPONENT
TIMING PARAMETERS
MODULE
MARKING
-13E
-133
-10E
-662
SPEED
GRADE
-7E
-75
-8E
-10
CAS
ACCESS
LATENCY TIME
2
3
2
2
5.4ns
5.4ns
6ns
9ns
SETUP
TIMES
1.5ns
1.5ns
2ns
3ns
HOLD
TIMES
0.8ns
0.8ns
1ns
1ns
PIN SYMBOL PIN
1
V
SS
43
2
DQ0
44
3
DQ1
45
4
DQ2
46
5
DQ3
47
6
V
DD
48
7
DQ4
49
8
DQ5
50
9
DQ6
51
10
DQ7
52
11
DQ8
53
12
V
SS
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
V
DD
60
19
DQ14
61
20
DQ15
62
21
NC
63
22
NC
64
23
V
SS
65
24
NC
66
25
NC
67
26
V
DD
68
27
WE#
69
28
DQMB0
70
29
DQMB1
71
30
S0#
72
31
DNU
73
32
V
SS
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
A10
80
39
BA1
81
40
V
DD
82
41
V
DD
83
42
CK0
84
**-133/-10E version only
NOTE:
SYMBOL
V
SS
DNU
S2#
DQMB2
DQMB3
DNU
V
DD
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC (CKE1)
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
NC/WP**
SDA
SCL
V
DD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
NC
NC
V
SS
NC
NC
V
DD
CAS#
DQMB4
DQMB5
NC (S1#)
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CK1
NC (A12)
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
CKE0
NC (S3#)
DQMB6
DQMB7
NC (A13)
V
DD
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
Pin symbols in parentheses are not used on these modules
but may be used for other modules in this product family.
They are for reference only.
4, 8 Meg x 64 SDRAM DIMMs
ZM16_4.p65 – Rev. 4/00a
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4, 8, 16 MEG x 64
SDRAM DIMMs
PART NUMBERS
PART NUMBER
CONFIGURATION
SYSTEM BUS SPEED
MT4LSDT464AG-13E_
MT4LSDT464AG-133_
MT4LSDT464AG-10E_
MT4LSDT464AG-662_
MT4LSDT864AG-13E_
MT4LSDT864AG-133_
MT4LSDT864AG-10E_
MT4LSDT1664AG-13E_
MT4LSDT1664AG-133_
MT4LSDT1664AG-10E
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
133MHz
133 MHz
100 MHz
66 MHz
133 MHz
133 MHz
100 MHz
133 MHz
100 MHz
133 MHz
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT4LSDT464AG-10EB2.
GENERAL DESCRIPTION
The MT4LSDT464A, MT4LSDT864A and
MT4LSDT1664A are high-speed CMOS, dynamic ran-
dom-access, 32MB, 64MB and 128MB memories orga-
nized in a x64 configuration. These modules use inter-
nally configured quad-bank SDRAMs with a synchro-
nous interface (all signals are registered on the positive
edge of the clock signals CK0,CK2).
Read and write accesses to the SDRAM modules are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0, BA1
select the bank, A0-A11 select the row). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the starting column location for
the burst access.
The modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full
page, with a burst terminate option. An atuo precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
These modules use an internal pipelined architec-
ture to achieve high-speed operation. This architecture
is compatible with the 2n rule of prefetch architectures,
but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully
random access. Precharging one bank while accessing
one of the other three banks will hide the precharge
cycles and provide seamless, high-speed, random-
access operation.
These modules are designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in
DRAM operating performance, including the ability to
syn-chronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal banks in order to hide
precharge time and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM
operation, refer to the 64Mb, 128Mb, or 256Mb SDRAM
data sheets.
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organization and timing parameters. The remaining
128 bytes of storage are available for use by the
customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
4, 8 Meg x 64 SDRAM DIMMs
ZM16_4.p65 – Rev. 4/00a
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4, 8, 16 MEG x 64
SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LSDT464A (32MB)/MT4LSDT864A (64MB)/MT4LSDT1664A (128MB)
S0#
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
S2#
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB2
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
RAS#
CAS#
CKE0
WE#
A0-A11
BA0-1
V
DD
V
SS
DQML CS#
DQ0
DQ1 U4
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML CS#
DQ0
DQ1 U1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQML CS#
DQ0
DQ1 U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQMB3
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQML CS#
DQ0
DQ1 U5
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMH
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RAS#: SDRAMs U1 U2,U4 U5
CAS#: SDRAMs U1,U2,U4,U5
CKE: SDRAMs U1 U2 U4,U5
WE#: SDRAMs U1,U2,U4 U5
A0-A11: SDRAMs U1,U2,U4,U5
BA0-1: SDRAMs U1,U2,U4,U5
SDRAMs U1,U2,U4,U5
SDRAMs U1,U2,U4,U5
SPD
CK1,CK2,CK3
CK1,CK3
CK0
U0
U1
U2
U3
CK2
CK0
U0
U1
13.4pF
U2
U3
13.6pF
SCL
WP
47K
A0
U6
A1
10pF
A2
SDA
10pF
100 MHz/133 MHz VERSIONS
66 MHz VERSION
SA0 SA1 SA2
U1,U2,U4,U5 = MT48LC4M16A2TG SDRAMs for 32MB
U1,U2,U4,U5 = MT48LC8M16A2TG SDRAMs for 64MB
U1,U2,U4,U5 = MT48LC16M16A2TG SDRAMs for 128MB
NOTE:
All resistor values are 10 ohms.
4, 8 Meg x 64 SDRAM DIMMs
ZM16_4.p65 – Rev. 4/00a
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4, 8, 16 MEG x 64
SDRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
115, 111, 27
42, 125, 79, 163
SYMBOL
RAS#, CAS#,
WE#
CK0-CK3
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS# and WE# (along with
S0#, S2#) define the command being entered.
Clock: CK0-CK3 are driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of CK. CK also increments the internal burst
counter and controls the output registers.
Clock Enable: CKE0 activates (HIGH) and deactivates
(LOW) the CK0-CK3 signals. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-
DOWN (row ACTIVE in any bank), or CLOCK SUSPEND
operation (burst access in progress). CKE0 is synchro-
nous except after the device enters power-down and
self refresh modes, where CKE0 becomes asynchro-
nous until after exiting the same mode. The input
buffers, including CK0-CK3, are disabled during
power-down and self refresh modes, providing low
standby power.
Chip Select: S0# and S2# enable (registered LOW)
and disable (registered HIGH) the command decoder.
All commands are masked when S0# and S2# are
registered HIGH. S0# and S2# are considered part of
the command code.
Input/Output Mask: DQMB is an input mask signal for
write accesses and an output enable signal for read
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when
DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
Address Inputs: A0-A12 are sampled during the
ACTIVE command (row-address A0-A12) and
READ/WRITE command (column-address A0-A7/A8
with A10 defining auto precharge) to select one
location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command
to determine if all banks are to be precharged (A10
HIGH) or bank selected by BA0, BA1 (LOW). The
address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Write Protect: Serial presence-detect hardware write
protect. Applies to -13E/-133/-10E versions only.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
128
CKE0
Input
30, 45
S0#, S2#
Input
28-29, 46-47,
112-113, 130-131
DQMB0-DQMB7
Input
122, 39
BA0, BA1
Input
33, 117, 34, 118, 35, 119,
36, 120, 37, 121, 38, 123,
126
A0-A12
Input
81
83
WP
SCL
Input
Input
4, 8 Meg x 64 SDRAM DIMMs
ZM16_4.p65 – Rev. 4/00a
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4, 8, 16 MEG x 64
SDRAM DIMMs
PIN DESCRIPTIONS (continued)
PIN NUMBERS
165-167
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95,
97-101, 103-104, 139-142,
144, 149-151, 153-156,
158-161
82
SYMBOL
SA0-SA2
DQ0-DQ63
TYPE
Input
Input/
Output
DESCRIPTION
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Data I/Os: Data bus.
SDA
Input/
Output
Supply
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
Power Supply: +3.3V ±0.3V.
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
31, 44, 48
V
DD
V
SS
Supply
Ground.
DNU
–
Do Not Use: These pins are not connected on this
module but are assigned pins on the compatible
DRAM version.
4, 8 Meg x 64 SDRAM DIMMs
ZM16_4.p65 – Rev. 4/00a
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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