531BB1406M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531BB1406M00DG

531BB1406M00DG: DescriptionLVDS Output Clock Oscillator, 1406MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531BB1406M00DG Overview

LVDS Output Clock Oscillator, 1406MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531BB1406M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1406 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

One of the thyristor excitation circuits of synchronous motors

DC bias magnetic system circuit

Circuit for measuring impact and tilt angle

Low power consumption four-level dimming circuit

TDA2822 power amplifier circuit

Frequency converter speed regulating circuit with main speed setting box and linkage setting operating box

Simple Oscilloscope Based on Single Chip Microcomputer: I want to use 89C52 + AD to make a simple oscilloscope. Has anyone in the forum done this before? Can you give me some advice?...; HSL199345 51mcu

【AT-START-F403A Review】2. Transplant AN0028--Locate HardFault (including simplified version project files): If a HardFault occurs when debugging a project, it will be a headache because it is difficult to track. I happened to like this APN0028 by Arteli, which talks about using cm_backtrace to help locate t...; mig29 Domestic Chip Exchange

Discussion post on VHDL small application design for FPGA. . . . .: I recently wrote a small piece of code and found a problem. It was running under my QUARTUSII9.0. I wrote a low-level module for a multi-person voter. When writing the VHDL code, I defined a sinual va...; shilaike FPGA/CPLD

【Silicon Labs Development Kit Review】Secure Code Testing: 1. Security procedures In the development of IoT applications, more and more security vulnerabilities are discovered, and camera hijacking has occurred many times. Therefore, adding security functions...; 北方 Development Kits Review Area

Wireless chip faster than 5G is born: Even before 5G becomes popular, researchers are already moving toward 6G. The next generation of mobile communications may require Tbps speeds, which far exceeds the theoretical capacity of 10 Gbps un...; ohahaha RF/Wirelessly

What are the functions of these two diodes and which models should be selected?: This circuit converts the three-wire signal of the synchro into a 2V sin and cos signal acceptable to AD2S83. The upper one is the reference voltage input. What is the role of the diode here? Should t...; 我爱一帆 Analog electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components