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85210AY-31LF

Description
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
Categorylogic    logic   
File Size132KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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85210AY-31LF Overview

Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

85210AY-31LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQFP-G32
JESD-609 codee3
length7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions2
Number of inverted outputs
Number of terminals32
Actual output times5
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP32,.35SQ,32
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup2 ns
propagation delay (tpd)2 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width7 mm
Base Number Matches1
ICS85210-31
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS85210-31 is a low skew, high performance
dual 1-to-5 Differential-to-HSTL Fanout Buffer.The
CLKx, nCLKx pairs can accept most standard differential
input levels. The ICS85210-31 is character ized to
operate from a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make
the ICS85210-31 ideal for those clock distribution
applications demanding well defined performance
and repeatability.
F
EATURES
Dual 1-to-5 HSTL compatible bank outputs
2 selectable differential clock input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
Maximum output frequency: 650MHz
Translates any single ended input signal to
LVHSTL levels with resistor bias on nCLKx inputs
Output skew: 50ps (maximum)
Part-to-part skew: 350ps (maximum)
Propagation delay: 2ns (maximum)
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
CLK0
nCLK0
QA0
nQA0
QA1
nQA1
CLK0_EN
D
Q
LE
QA2
nQA2
QA3
nQA3
QA4
nQA4
P
IN
A
SSIGNMENT
nQA0
nQA1
nQA2
V
DDO
V
DDO
QA0
QA1
QA2
32 31 30 29 28 27 26 25
V
DD
CLK0_EN
CLK0
nCLK0
CLK1_EN
CLK1
nCLK1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DDO
nQB4
QB4
nQB3
QB3
nQB2
QB2
V
DDO
24
23
22
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
ICS85210-31
21
20
19
18
17
CLK1
nCLK1
QB0
nQB0
QB1
nQB1
GND
CLK1_EN
D
Q
LE
QB2
nQB2
QB3
nQB3
QB4
nQB4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
85210AY-31
www.idt.com
1
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