874S02BMIT datasheet, PDF - EEWORLD Datasheet

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874S02BMIT: DescriptionPLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20; Categorylogic logic; File Size4MB，16 Pages; ManufacturerIDT (Integrated Device Technology)

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874S02BMIT Overview

PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20

874S02BMIT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20
Contacts	20
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	874S
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	1
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
minfmax	62.5 MHz
Base Number Matches	1

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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

ICS874S02I

General Description

The ICS874S02I is a highly versatile 1:1 Differential-

to-LVDS Clock Generator and a member of the

HiPerClockS™

HiPerClockS™ family of High Performance Clock

Solutions from IDT. The ICS874S02I has a fully

integrated PLL and can be configured as a zero

delay buffer, multiplier or divider, and has an output frequency

range of 62.5MHz to 1GHz. The reference divider, feedback

divider and output divider are each programmable, thereby

allowing for the following output-to-input frequency ratios: 8:1, 4:1,

2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to

achieve “zero delay” between the input clock and the output

clocks. The PLL_SEL pin can be used to bypass the PLL for

system test and debug purposes. In bypass mode, the reference

clock is routed around the PLL and into the internal output

dividers.

Features

•

One differential LVDS output pair and

one differential feedback output pair

One differential clock input pair

CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL

Input frequency range: 62.5MHz to 1GHz

Output frequency range: 62.5MHz to 1GHz

VCO range: 500MHz - 1GHz

External feedback for "zero delay" clock regeneration with

configurable frequencies

Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

Cycle-to-cycle jitter: 35ps (maximum)

Static phase offset: ±100ps

Full 3.3V supply mode

-40°C to 85°C ambient operating temperature

Available in standard (RoHS 5) package

ICS

Block Diagram

PLL_SEL

Pullup

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

Pin Assignment

QFB

nQFB

CLK

nCLK

nFB_IN

FB_IN

SEL2

DDO

nQFB

QFB

GND

SEL1

SEL0

PLL_SEL

DDA

SEL3

GND

DDO

CLK

Pulldown

nCLK

Pullup

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

FB_IN

Pulldown

nFB_IN

Pullup

ICS874S02I

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm package body

M Package

Top View

SEL0

Pulldown

SEL1

Pulldown

SEL2

Pulldown

SEL3

Pulldown

IDT™ / ICS™

LVDS CLOCK GENERATOR

ICS874S02BMI REV. AOCTOBER 16, 2008

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