÷1/÷2 Differential-to-LVDS
Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
Data Sheet
87421
G
ENERAL
D
ESCRIPTION
The 87421I is a high performance ÷1/÷2
Differential-to-LVDS Clock Generator. The CLK, nCLK
p a i r c a n a c c e p t m o s t s t a n d a r d d i f fe r e n t i a l i n p u t
levels. The 87421I is characterized to operate from a 3.3V
power supply. Guaranteed part-to-part skew characteristics
make the 87421I ideal for those clock distribution applications
demanding well defined performance and repeatability.
F
EATURES
• One differential LVDS output
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input lev-
els: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
•
For functional replacement device use 87321
B
LOCK
D
IAGRAM
÷1
CLK
nCLK
P
IN
A
SSIGNMENT
0
1
Q
nQ
CLK
nCLK
MR
F_SEL
1
2
3
4
8
7
6
5
V
DD
Q
nQ
GND
R ÷2
MR
87421I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
F_SEL
©2016 Integrated Device Technology, Inc
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June 24, 2016
87421 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
Name
CLK
nCLK
MR
Input
Input
Input
Type
Pullup
Description
Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output (Q) to go low and the inverted output (nQ)
Pulldown
to go high. When logic LOW, the internal dividers and the output are
enabled. LVCMOS / LVTTL interface levels. See Table 3.
Selects divider value for Q, nQ outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Positive supply pin.
4
5
6, 7
8
F_SEL
GND
Q, nQ
V
DD
Input
Power
Output
Power
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. F
UNCTION
T
ABLE
MR
1
0
0
F_SEL
X
0
1
Divide Value
Reset: Q output low, nQ output high
÷1
÷2
CLK
MR
Q
F
IGURE
1A. ÷1 C
ONFIGURATION
T
IMING
D
IAGRAM
F
IGURE
1B. ÷2 C
ONFIGURATION
T
IMING
D
IAGRAM
©2016 Integrated Device Technology, Inc
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June 24, 2016
87421 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
96°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
55
Maximum
3.465
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
MR, F_SEL
MR, F_SEL
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
1.37
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1
NOTE 1: Common mode voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
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June 24, 2016
87421 Data Sheet
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
350
1.1
Typical
470
1.25
Maximum
540
50
1.4
50
Units
mV
mV
V
mV
V
OS
Δ
V
OS
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
CLK
t
PD
tsk(pp)
t
JIT
t
R
/ t
F
odc
Parameter
Clock Input Frequency
Propagation Delay;
NOTE 1
CLK to Q (Dif)
1.0
Test Conditions
Minimum
Typical
Maximum
1
1.7
500
155.52MHz, Integration Range:
12kHz – 20MHz
20% to 80%
f
IN
< 500MHz
150
43
0.17
500
57
Units
GHz
ns
ps
ps
ps
%
Part-to-Part Skew; NOTE 2, 3
Additive Phase Noise, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
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June 24, 2016
87421 Data Sheet
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@
155.52MHz (12kHz to 20MHz) = 0.17ps typical
SSB P
HASE
N
OISE
dBc/H
Z
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements have
issues. The primary issue relates to the limitations of the equipment.
Often the noise floor of the equipment is higher than the noise floor
of the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise
is dependant on the input source and measurement equipment.
©2016 Integrated Device Technology, Inc
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June 24, 2016
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