HITACHI SINGLE-CHIP MICROCOMPUTER
H8/330
HD6473308, HD6433308, HD6413308
HARDWARE MANUAL
Preface
The H8/330 is a high-performance single-chip microcomputer ideally suited for embedded control
of industrial equipment. Its core is the H8/300 CPU: a high-speed processor. On-chip supporting
modules provide memory, I/O, and timer functions, including:
• 16K bytes of on-chip ROM
• 512 bytes of on-chip RAM
• 15 bytes of dual-port RAM for a master-slave interface
• Serial I/O
• General-purpose I/O ports
• A/D converter
• Timers
Compact, high-performance control systems can be built using the H8/330.
The H8/330 is available with either electrically programmable or mask programmable ROM.
Manufacturers can use the electrically programmable ZTAT™* (Zero Turn-Around Time) version
to get production off to a fast start and make software changes quickly, then switch over to the
masked version for full-scale production runs.
This manual describes the H8/330 hardware. Refer to the
H8/300 Series Programming Manual
for
a detailed description of the instruction set.
* ZTAT is a registered trademark of Hitachi, Ltd.
CONTENTS
Section 1. Overview
............................................................................................................... 1
1.1
1.2
1.3
Block Diagram......................................................................................................................
Descriptions of Blocks..........................................................................................................
Pin Assignments and Functions............................................................................................
1.3.1 Pin Arrangement......................................................................................................
1.3.2 Pin Functions ...........................................................................................................
2
3
6
6
9
Section 2. MCU Operating Modes and Address Space
................................................ 17
2.1
2.2
2.3
Overview...............................................................................................................................
Mode Descriptions................................................................................................................
Address Space Map ..............................................................................................................
2.3.1 Access Speed ...........................................................................................................
2.3.2 IOS...........................................................................................................................
Mode and System Control Registers (MDCR and SYSCR).................................................
2.4.1 Mode Control Register (MDCR) – H'FFC5 ............................................................
2.4.2 System Control Register (SYSCR) – H'FFC4.........................................................
17
18
19
19
19
21
21
22
2.4
Section 3. CPU
........................................................................................................................ 25
3.1
3.2
Overview............................................................................................................................... 25
3.1.1 Features.................................................................................................................... 25
Register Configuration.......................................................................................................... 26
3.2.1 General Registers.....................................................................................................
3.2.2 Control Registers .....................................................................................................
3.2.3 Initial Register Values..............................................................................................
Addressing Modes ................................................................................................................
Data Formats.........................................................................................................................
3.4.1 Data Formats in General Registers..........................................................................
3.4.2 Memory Data Formats.............................................................................................
Instruction Set .......................................................................................................................
3.5.1 Data Transfer Instructions .......................................................................................
3.5.2 Arithmetic Operations .............................................................................................
3.5.3 Logic Operations .....................................................................................................
3.5.4 Shift Operations.......................................................................................................
3.5.5 Bit Manipulations ....................................................................................................
3.5.6 Branching Instructions.............................................................................................
3.5.7 System Control Instructions ....................................................................................
26
27
28
29
31
32
33
34
36
38
39
39
41
47
49
3.3
3.4
3.5
i
3.6
3.7
3.5.8 Block Data Transfer Instruction ..............................................................................
CPU States ............................................................................................................................
3.6.1 Program Execution State .........................................................................................
3.6.2 Exception-Handling State........................................................................................
3.6.3 Power-Down State ...................................................................................................
Access Timing and Bus Cycle ..............................................................................................
3.7.1 Access to On-Chip Memory (RAM and ROM) ......................................................
3.7.2 Access to On-Chip Register Field and External Devices ........................................
50
51
52
52
53
53
53
55
Section 4. Exception Handling
............................................................................................ 59
4.1
4.2
Reset .....................................................................................................................................
Interrupts...............................................................................................................................
4.2.1 Interrupt-Related Registers......................................................................................
4.2.2 External Interrupts ...................................................................................................
4.2.3 Internal Interrupts ....................................................................................................
4.2.4 Interrupt Response Time..........................................................................................
4.2.5 Note on Stack Handling...........................................................................................
4.2.6 Deferring of Interrupts.............................................................................................
60
63
69
70
71
72
73
75
Section 5. I/O Ports
................................................................................................................ 77
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Overview............................................................................................................................... 77
Port 1..................................................................................................................................... 78
Port 2..................................................................................................................................... 81
Port 3..................................................................................................................................... 84
Port 4..................................................................................................................................... 88
Port 5..................................................................................................................................... 91
Port 6..................................................................................................................................... 96
Port 7..................................................................................................................................... 102
Port 8..................................................................................................................................... 104
Port 9..................................................................................................................................... 114
Section 6. 16-Bit Free-Running Timer
.............................................................................. 123
6.1
Overview............................................................................................................................... 123
6.1.1 Features.................................................................................................................... 123
6.1.2 Block Diagram......................................................................................................... 123
6.1.3 Input and Output Pins .............................................................................................. 125
6.1.4 Register Configuration ............................................................................................ 125
Register Descriptions............................................................................................................ 126
6.2
ii
6.3
6.4
6.5
6.6
6.7
Free-Running Counter (FRC) – H'FF92.................................................................. 126
Output Compare Registers A and B (OCRA and OCRB) – H'FF94....................... 127
Input Capture Registers A to D (ICRA to ICRD) –
H'FF98, H'FF9A, H'FF9C, H'FF9E ......................................................................... 127
6.2.4 Timer Interrupt Enable Register (TIER) – H'FF90 ................................................. 129
6.2.5 Timer Control/Status Register (TCSR) – H'FF91 ................................................... 131
6.2.6 Timer Control Register (TCR) – H'FF96 ................................................................ 134
6.2.7 Timer Output Compare Control Register (TOCR) – H'FF97.................................. 136
CPU Interface ....................................................................................................................... 137
Operation .............................................................................................................................. 139
6.4.1 FRC Incrementation Timing.................................................................................... 139
6.4.2 Output Compare Timing.......................................................................................... 141
6.4.3 Input Capture Timing .............................................................................................. 142
6.4.4 Setting of FRC Overflow Flag (OVF)..................................................................... 145
Interrupts............................................................................................................................... 146
Sample Application............................................................................................................... 146
Application Notes ................................................................................................................. 147
6.2.1
6.2.2
6.2.3
Section 7. 8-Bit Timers
......................................................................................................... 153
7.1
Overview............................................................................................................................... 153
7.1.1 Features.................................................................................................................... 153
7.1.2 Block Diagram......................................................................................................... 153
7.1.3 Input and Output Pins .............................................................................................. 154
7.1.4 Register Configuration ............................................................................................ 155
Register Descriptions............................................................................................................ 155
7.2.1 Timer Counter (TCNT) – H'FFC8 (TMR0), H'FFD0 (TMR1) ............................... 155
7.2.2 Time Constant Registers A and B (TCORA and TCORB) –
H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1) .............................. 156
7.2.3 Timer Control Register (TCR) – H'FFC8 (TMR0), H'FFD0 (TMR1) .................... 156
7.2.4 Timer Control/Status Register (TCSR) – H'FFC9 (TMR0), H'FFD1 (TMR1) ....... 158
Operation .............................................................................................................................. 160
7.3.1 TCNT Incrementation Timing................................................................................. 160
7.3.2 Compare Match Timing........................................................................................... 161
7.3.3 External Reset of TCNT .......................................................................................... 163
7.3.4 Setting of TCSR Overflow Flag .............................................................................. 164
Interrupts............................................................................................................................... 165
Sample Application............................................................................................................... 165
Application Notes ................................................................................................................. 166
7.2
7.3
7.4
7.5
7.6
iii
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