EEWORLDEEWORLDEEWORLD

Part Number

Search

531PB159M000BGR

Description
CMOS Output Clock Oscillator, 159MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size268KB,15 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

531PB159M000BGR Overview

CMOS Output Clock Oscillator, 159MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531PB159M000BGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency159 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
physical size7.0mm x 5.0mm x 1.85mm
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.0 7/06
Copyright © 2006 by Silicon Laboratories
Si530/531
Please come in, Mr.
I have a question. I am using stm32f103zet6. If I define a variable in external RAM, what keyword should I add before the variable? Please give an example. Thank you....
GZCYGS stm32/stm8
How to Use Quartus II
I am not very familiar with the interface of Quartus II. I have written source code in Verilog HDL language and want to implement logic functions directly through code generation. I don’t know where t...
果果女 Embedded System
Module Power Structure Design Guide
The main form of module power supply is DC-DC module, in addition there are AC-DC module, DC-AC (ring current) module. Unless otherwise specified, this article assumes DC-DC module....
鬼谷清泉 Power technology
Xilinx Spartan-6 LX9 Development Board Trial Summary
Thank you very much to the moderator and EE for providing this opportunity, and thank you to maylove for your understanding. The following is a summary of this trial.1) The DEMO program included with ...
lylyhs FPGA/CPLD
Why does the value of my AD collection jitter so much, and each AD port interferes with each other?
//Although the corresponding ad value will change when adjusting the resistance of port A0, the values of other ports will also change, but the amplitude is not as large as port A0. void adc_init(void...
one55 Microcontroller MCU
I hope you can give me some information about ultrasonic ranging.
[i=s]This post was last edited by paulhyde on 2014-9-15 09:07[/i] I want to make an ultrasonic distance measurement module recently, but I don't know which chip and circuit diagram are more suitable. ...
tokychen Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 495  1138  2625  414  800  10  23  53  9  17 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号