Product Specification
PE3336
Product Description
Peregrine’s PE3336 is a high performance integer-N PLL
capable of frequency synthesis up to 3 GHz. The superior
phase noise performance of the PE3336 makes it ideal for
applications such as LMDS / MMDS / WLL basestations
and demanding terrestrial systems.
The PE3336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in
Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE3336 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
3 GHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Features
3 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel or hardwired
programmable
Pin compatible with PE3236
Ultra-low phase noise
Available in a 7 x 7 mm 48-lead QFN
green (RoHS-Compliant) package
Figure 1. Block Diagram
Document No. 70-0033-05
│
www.psemi.com
O
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
bs
o
le
te
PE3336
Product Specification
Figure 2. Pin Configurations (Top View)
GND
GND
GND
48 47 46 45 44 43 42 41 40 39 38 37
D0, M0
D1, M1
D2, M2
D3, M3
V
DD
V
DD
S_WR, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
FSELP, A0
1
2
3
4
5
6
7
8
9
10
11
12
GND
Enh
V
DD
LD
R3
R2
R1
R0
f
r
36
35
34
33
32
31
30
29
28
27
26
25
f
c
V
DD
_f
c
NC
PD_U
PD_D
GND
V
DD
C
ext
V
DDE
D
out
V
DD
_f
p
f
p
13 14 15 16 17 18 19 20 21 22 23 24
E_WR, A1
M2_WR, A2
Smode, A3
Bmode
V
DD
V
DD
M1_WR
A_WR
Hop_WR
Fin
Fin
GND
48-lead QFN (RoHS-Compliant)
Table 1. Pin Descriptions
Pin No.
1
M
0
D
1
2
M
1
D
2
3
M
2
D
3
4
M
3
5
6
V
DD
V
DD
Direct
ALL
ALL
Input
(Note 1)
(Note 1)
Direct
Parallel
Direct
Pin Name
D
0
Interface Mode
Parallel
bs
o
Type
Input
Input
Input
Input
Input
Input
Input
le
Description
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing rec-
ommended.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing rec-
ommended.
Document No. 70-0033-05
│
UltraCMOS™ RFIC Solutions
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
O
Parallel
Direct
Parallel
te
PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
S_WR
7
D
4
M
4
Sdata
8
D
5
M
5
Sclk
9
D
6
M
6
FSELS
10
D
7
Pre_en
11
GND
FSELP
12
A
0
Direct
Serial
E_WR
13
A
1
M2_WR
14
A
2
Smode
15
A
3
16
17,18
19
20
21
22
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
Direct
ALL
ALL
Parallel
Parallel
Serial, Parallel
ALL
Input
Input
(Note 1)
Input
Input
Input
Input
Direct
Serial, Parallel
Input
Input
Parallel
Direct
Parallel
Direct
ALL
Parallel
Input
Input
Parallel
Direct
Serial
Input
Input
Input
Parallel
Direct
Serial
Parallel
Direct
Serial
Input
Input
Input
Input
Input
Input
Interface Mode
Serial
Type
Input
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially
clocked. Primary register data are transferred to the secondary register on
S_WR or Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
Parallel data bus bit6.
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
O
Parallel
Document No. 70-0033-05
│
www.psemi.com
bs
o
Input
Input
Input
Input
Input
Input
le
Ground.
A Counter bit1.
A Counter bit2.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement
register on the rising edge of E_WR.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
Selects serial bus interface mode (Bmode=0,
Smode=1)
or Parallel Interface
Mode (Bmode=0,
Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
M1 write. D[7:0] are latched into the primary register (Pre_en,
M[6:0]) on
the rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
te
M Counter bit6.
PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
23
24
25
Pin Name
F
in
GND
f
p
Interface Mode
ALL
ALL
ALL
Output
Type
Input
Description
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50
Ω
resistor
directly to the ground plane.
Ground.
Monitor pin for main divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding V
DD
pin 31.
V
DD
for f
p
. Can be left floating or connected to GND to disable the f
p
output.
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
26
27
28
V
DD
-f
p
Dout
V
DD
ALL
Serial, Parallel
ALL
(Note 1)
Output
(Note 1)
29
Cext
ALL
Output
30
32
33
34
35
36
31,37
38,39
40
41
42
43
44
45
46
47
48
V
DD
PD_D
PD_U
NC
V
DD
-f
c
f
c
GND
GND
f
r
LD
Enh
V
DD
R
0
R
1
R
2
R
3
GND
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Serial, Parallel
ALL
Direct
Direct
Direct
Direct
ALL
(Note 1)
Output
O
Notes: 1. All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
V
DD
-f
p
and V
DD
-f
p
are used to power the f
p
and f
c
outputs and can alternatively be left floating or connected to GND to disable the f
p
and f
c
outputs.
2. All digital input pins have 70 kΩ pull-down resistors to ground.
bs
o
(Note 1)
Output
Input
Output
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
le
No connection.
Ground.
Ground.
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
PD_D is pulse down when f
p
leads f
c
.
PD_U is pulse down when f
c
leads f
p
.
V
DD
for f
c
can be left floating or connected to GND to disable the f
c
output.
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding V
DD
pin 38.
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When the loop is in
lock, LD is high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits
are functional.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0 (LSB).
te
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
Document No. 70-0033-05
│
UltraCMOS™ RFIC Solutions
PE3336
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+
0.3
+10
+10
150
Units
V
V
mA
mA
°C
Table 4. ESD Ratings
Symbol
V
ESD
Parameter/Conditions
ESD voltage (Human Body
Model)
Level
1000
Units
V
Note: Periodically sampled, not 100% tested. Tested per MIL-STD-883, M3015 C2
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°C
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in
Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics:
V
DD
= 3.0 V, -40 °C < T
A
< 85 °C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler disabled
Prescaler enabled
Conditions
Min
Typ
10
19
Max
Units
mA
mA
bs
o
le
V
DD
= 2.85 to 3.15 V
te
-1
-5
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE3336 is MSL3.
26
Digital Inputs: All except f
r
, R
0
, F
in
,
F
in
V
IH
V
IL
I
IH
I
IL
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
0.7 x V
DD
0.3 x V
DD
+70
V
V
μA
μA
Reference Divider input: f
r
I
IHR
I
ILR
O
High level input current
Low level input current
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
100
μA
μA
R0 Input (Pull-up Resistor): R
0
I
IHRO
I
ILRO
High level input current
Low level input current
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
5
μA
μA
Counter and phase detector outputs: f
c
, f
p
, PD_D,
PD_U
V
OLD
V
OHD
Output voltage LOW
Output voltage HIGH
I
out
= 6 mA
I
out
= -3 mA
V
DD
- 0.4
0.4
V
V
Lock detect outputs: Cext, LD
V
OLC
V
OHC
V
OLLD
Output voltage LOW, Cext
Output voltage HIGH, Cext
Output voltage LOW, LD
I
out
= 100 mA
I
out
= -100 mA
I
out
= 6 mA
V
DD
- 0.4
0.4
0.4
V
V
V
Document No. 70-0033-05
│
www.psemi.com
©2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
京公网安备 11010802033920号
EEWORLD
