IDT71321LA35J datasheet, PDF - EEWORLD Datasheet

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IDT71321LA35J: DescriptionDual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52; Categorystorage storage; File Size190KB，13 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71321LA35J Overview

Dual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52

IDT71321LA35J Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
Contacts	52
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	35 ns
Other features	INTERRUPT FLAG; AUTOMATIC POWER-DOWN; BATTERY BACKUP
I/O type	COMMON
JESD-30 code	S-PQCC-J52
JESD-609 code	e0
length	19.1262 mm
memory density	16384 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	52
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.0015 A
Minimum standby current	2 V
Maximum slew rate	0.12 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	19.1262 mm
Base Number Matches	1

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HIGH-SPEED 2K x 8

DUAL-PORT STATIC RAM

WITH INTERRUPTS

Integrated Device Technology, Inc.

IDT71321SA/LA

IDT71421SA/LA

FEATURES:

• High-speed access

—Commercial: 20/25/35/45/55ns (max.)

• Low-power operation

—IDT71321/IDT71421SA

—Active:

550mW (typ.)

—Standby:

5mW (typ.)

—IDT71321/421LA

—Active:

550mW (typ.)

—Standby:

1mW (typ.)

• Two

INT

flags for port-to-port communications

• MASTER IDT71321 easily expands data bus width to 16-

or-more-bits using SLAVE IDT71421

• On-chip port arbitration logic (IDT71321 only)

•

BUSY

output flag on IDT71321;

BUSY

input on IDT71421

• Fully asynchronous operation from either port

• Battery backup operation —2V data retention (LA Only)

• TTL-compatible, single 5V

±10%

power supply

• Available in popular hermetic and plastic packages

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT71321/IDT71421 are high-speed 2K x 8 Dual-

Port Static RAMs with internal interrupt logic for interproces-

sor communications. The IDT71321 is designed to be used

as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"

Dual-Port RAM together with the IDT71421 "SLAVE" Dual-

Port in 16-bit-or-more word width systems. Using the IDT

MASTER/SLAVE Dual-Port RAM approach in 16-or-more-

bit memory system applications results in full speed, error-

free operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa-

rate control, address, and I/O pins that permit independent,

asynchronous access for reads or writes to any location in

memory. An automatic power down feature, controlled by

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance technol-

ogy, these devices typically operate on only 550mW of

power. Low-power (LA) versions offer battery backup data

retention capability, with each Dual-Port typically consum-

ing 200µW from a 2V battery.

The IDT71321/IDT71421 devices are packaged in a 52-

pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.

FUNCTIONAL BLOCK DIAGRAM

I/O

- I/O

I/O

Control

I/O

Control

I/O

-I/O

BUSY

(1,2)

BUSY

Address

Decoder

(1,2)

10L

MEMORY

ARRAY

Address

Decoder

10R

NOTES:

1. IDT71321 (MASTER):

BUSY

is open drain output and

requires pullup resistor of 270Ω.

IDT71421 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup

resistor of 270Ω.

INT

ARBITRATION

and

INTERRUPT

LOGIC

(2)

INT

(2)

2691 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

OCTOBER 1996

DSC-2691/6

6.03

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