IDT7005S55JB datasheet, PDF - EEWORLD Datasheet

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IDT7005S55JB: DescriptionDual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68; Categorystorage storage; File Size261KB，20 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT7005S55JB Overview

Dual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68

IDT7005S55JB Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	not_compliant
ECCN code	3A001.A.2.C
Maximum access time	55 ns
I/O type	COMMON
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
length	24.2062 mm
memory density	65536 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of ports	2
Number of terminals	68
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.03 A
Minimum standby current	4.5 V
Maximum slew rate	0.3 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.2062 mm
Base Number Matches	1

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HIGH-SPEED

8K x 8 DUAL-PORT

STATIC RAM

Integrated Device Technology, Inc.

IDT7005S/L

FEATURES:

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• High-speed access

— Military: 20/25/35/55/70ns (max.)

— Commercial:15/17/20/25/35/55ns (max.)

• Low-power operation

— IDT7005S

Active: 750mW (typ.)

Standby: 5mW (typ.)

— IDT7005L

Active: 750mW (typ.)

Standby: 1mW (typ.)

• IDT7005 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading

more than one device

• M/

= H for

BUSY

output flag on Master,

= L for

BUSY

input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of Semaphore signaling

between ports

• Fully asynchronous operation from either port

• Devices are capable of withstanding greater than 2001V

electrostatic discharge

• Battery backup operation—2V data retention

• TTL-compatible, single 5V (±10%) power supply

• Available in 68-pin PGA, 68-pin quad flatpack, 68-pin

PLCC, and a 64-pin TQFP

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM.

The IDT7005 is designed to be used as a stand-alone Dual-

Port RAM or as a combination MASTER/SLAVE Dual-Port

FUNCTIONAL BLOCK DIAGRAM

I/O

- I/O

I/O

Control

I/O

Control

I/O

-I/O

BUSY

(1,2)

BUSY

Address

Decoder

(1,2)

12L

MEMORY

ARRAY

Address

Decoder

12R

NOTES:

1. (MASTER):

BUSY

is output;

(SLAVE):

BUSY

is input.

BUSY

outputs

and

INT

outputs

are non-tri-stated

push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEM

(2)

SEM

(2)

INT

2738 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

OCTOBER 1996

DSC-2738/6

6.06

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