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709279L15PF8

Description
TQFP-100, Reel
Categorystorage    storage   
File Size309KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
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709279L15PF8 Overview

TQFP-100, Reel

709279L15PF8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTQFP
package instruction14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts100
Manufacturer packaging codePN100
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.B
Maximum access time30 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)40 MHz
I/O typeCOMMON
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply5 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.005 A
Minimum standby current4.5 V
Maximum slew rate0.285 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
Base Number Matches1
HIGH-SPEED 32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
*SPECIFIED PART IS OBSOLETE NOT RECOMMENDED FOR NEW DESIGNS
709279
*709269S/L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT709279/69S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709279/69L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pin
Dual chip enables allow for depth expansion without
additional logic
Counter enable and reset features
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 67MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available. See ordering information
Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience.
Functional Block Diagram
R/W
L
UB
L
CE
0L
CE
1L
LB
L
OE
L
1
0
0/1
1
0
0/1
R/W
R
UB
R
CE
0R
CE
1R
LB
R
OE
R
FT/PIPE
L
I/O
8L
-
I/O
15L
I/O
0L
-I/O
7L
0/1
1b 0b b a 1a 0a
0a 1a
a
b 0b 1b
0/1
FT/PIPE
R
I/O
8R
-I/O
15R
,
,
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
A
14L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
NOTE:
1. A
14X
is a NC for IDT709269.
A
14R
(1)
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3243 drw 01
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-3243/16
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