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7130SA35JB

Description
Dual-Port SRAM, 1KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
Categorystorage    storage   
File Size153KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

7130SA35JB Overview

Dual-Port SRAM, 1KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52

7130SA35JB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instructionQCCJ, LDCC52,.8SQ
Contacts52
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeS-PQCC-J52
JESD-609 codee0
length19.1262 mm
memory density8192 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals52
word count1024 words
character code1000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize1KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC52,.8SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Filter levelMIL-PRF-38535
Maximum seat height4.57 mm
Maximum standby current0.03 A
Minimum standby current4.5 V
Maximum slew rate0.23 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width19.1262 mm
Base Number Matches1
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT7130/IDT7140LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
IDT7130SA/LA
IDT7140SA/LA
On-chip port arbitration logic (IDT7130 Only)
BUSY
output flag on IDT7130;
BUSY
input on IDT7140
INT
flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
10
,
(1,2)
A
9L
A
0L
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2689 drw 01
(2)
NOTES:
1. IDT7130 (MASTER):
BUSY
is open drain output and requires pullup resistor.
IDT7140 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor.
JANUARY 2002
1
DSC-2689/11
©2002 Integrated Device Technology, Inc.
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