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74F280SJX_NL

Description
Parity Generator/Checker, TTL, PDSO14,
Categorylogic    logic   
File Size73KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric View All

74F280SJX_NL Overview

Parity Generator/Checker, TTL, PDSO14,

74F280SJX_NL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
package instructionSOP, SOP14,.3
Reach Compliance Codecompliant
JESD-30 codeR-PDSO-G14
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply5 V
Certification statusNot Qualified
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Base Number Matches1
74F280 9-Bit Parity Generator/Checker
April 1988
Revised September 2000
74F280
9-Bit Parity Generator/Checker
General Description
The F280 is a high-speed parity generator/checker that
accepts nine bits of input data and detects whether an
even or an odd number of these inputs is HIGH. If an even
number of inputs is HIGH, the Sum Even output is HIGH. If
an odd number is HIGH, the Sum Even output is LOW. The
Sum Odd output is the complement of the Sum Even out-
put.
Ordering Code:
Order Number
74F280SC
74F280SJ
74F280PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009512
www.fairchildsemi.com
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