PHKD6N02LT
Dual TrenchMOS™ logic level FET
M3D315
Rev. 02 — 12 August 2003
Product data
1. Description
Dual N-channel enhancement mode field-effect transistors in a plastic surface mount
package using TrenchMOS™ technology.
Product availability:
PHKD6N02LT in SOT96-1 (SO8).
2. Features
s
s
s
s
Low on-state resistance
Logic level compatible
Dual device
Surface mount package.
3. Applications
s
s
s
s
DC-to-DC converters
Notebook computers
Portable appliances
Battery chargers.
4. Pinning information
Table 1:
Pin
1
2
3
4
5, 6
7, 8
Pinning - SOT96-1 (SO8), simplified outline and symbol
Description
source1 (s1)
gate1 (g1)
source2 (s2)
gate2 (g2)
drain2 (d2)
drain1 (d1)
1
Top view
4
MBK187
Simplified outline
8
5
Symbol
d1 d1
d2 d2
SOT96-1 (SO8)
s1
g
1
s2
g
2
MBK725
Philips Semiconductors
PHKD6N02LT
Dual TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
25
°C ≤
T
j
≤
150
°C
T
sp
= 25
°C
T
sp
= 25
°C
V
GS
= 5 V; I
D
= 3 A
V
GS
= 2.5 V; I
D
= 3 A
[1]
Single device conducting.
[1]
Symbol Parameter
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Typ
-
-
-
-
16
25
Max
20
10.9
4.17
150
20
35
Unit
V
A
W
°C
mΩ
mΩ
6. Ordering information
Table 3:
Ordering information
Package
Name
PHKD6N02LT
SO8
Description
Plastic small outline package; 8 leads
Version
SOT96-1
Type number
7. Limiting values
Table 4:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
peak (diode forward) source current T
sp
= 25
°C;
t
p
≤
10
µs
[1]
Single device conducting.
Conditions
T
j
= 25 to 150
°C
T
j
= 25 to 150
°C;
R
GS
= 20 kΩ
T
sp
= 25
°C;
Figure 2
and
3
T
sp
= 100
°C;
Figure 2
T
sp
= 25
°C;
t
p
≤
100
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
[1]
[1]
[1]
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
20
20
±12
10.9
6.8
44
4.17
+150
+150
3.5
44
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain (reverse) diode
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
2 of 12
Philips Semiconductors
PHKD6N02LT
Dual TrenchMOS™ logic level FET
120
Pder
(%)
80
03aa17
120
Ider
(%)
80
03aa25
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp (
°
C)
V
GS
≥
4.5 V
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
003aaa300
Limit RDSon = VDS/ID
ID
(A)
10
tp = 10
µs
100
µs
1 ms
10 ms
100 ms
DC
1
10-1
10-2
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
3 of 12
Philips Semiconductors
PHKD6N02LT
Dual TrenchMOS™ logic level FET
8. Thermal characteristics
Table 5:
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
minimum footprint;
mounted on printed-circuit board
Min Typ Max
-
-
-
70
30
-
Unit
K/W
K/W
thermal resistance from junction to solder point
thermal resistance from junction to ambient
Symbol Parameter
8.1 Transient thermal impedance
102
Zth(j-sp)
(K/W)
δ
= 0.5
10
0.2
0.1
0.05
0.02
1
P
single pulse
003aaa301
δ
=
tp
T
tp
10-1
10-4
T
10-3
10-2
10-1
1
tp (s)
t
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
4 of 12
Philips Semiconductors
PHKD6N02LT
Dual TrenchMOS™ logic level FET
9. Characteristics
Table 6:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
I
D
= 250
µA;
V
GS
= 0 V
I
D
= 250
µA;
V
DS
= 10 V;
Figure 9
V
DS
= 20 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±12
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 3 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 2.5 V; I
D
= 3 A
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 6 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 6 A; dI
S
/dt =
−100
A/µs; V
R
= 20 V;
V
GS
= 0 V
V
DS
= 10 V; R
D
= 3.3
Ω;
V
GS
= 5 V; R
G
= 4.7
Ω
V
GS
= 0 V; V
DD
= 10 V; f = 1 MHz;
Figure 11
I
D
= 6 A; V
DD
= 16 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
15.3
2.2
6
950
355
256
15
49
50
23
-
40
7
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
16
-
25
20
35
35
mΩ
mΩ
mΩ
-
-
-
0.05
-
-
10
500
µA
µA
20
0.5
-
-
-
1.5
V
V
Conditions
Min
Typ
Max
Unit
±100
nA
Source-drain (reverse) diode
9397 750 10688
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 12 August 2003
5 of 12
Power technology
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